Bluespec: Why chip design can't be left EE's - MIT

More documents

Recommendations

Info

IA64 Modeling in Bluespec CMU-Intel collaboration Develop an Itanium µarch model that is concise and malleable executable and synthesizable FPGA Prototyping XC2V6000 FPGA interfaced to P6 memory bus Executes binaries natively against a real PC environment (i.e., memory & I/O devices) An evaluation vehicle for: Functionality and performance: a fast µarchitecture emulator to run real software Implementation: a synthesizable description to assess feasibility, design complexity and implementation cost Roland Wunderlich & James Hoe @ CMU Steve Hynal(SCL) & Shih-Lien Liu(MRL) 22
The “Arbiter” Project @ Sandburst Apples-to-apples comparison Re-code product chip (“arbiter”) in Bluespec 2 Bluespec engineers, 2 ASIC designers; 9/1/02 to 12/31/02 (all of them on a learning curve) Completed synthesis, test insertion, physical layout, timing analysis on each sub block (hard macro) Comparison with Verilog for Multicast Arbiter Speed Area Lines of code Verification Architectural Exploration Both met goal: 200MHz Both ~ 1.55M gates Multicast arbiter: 19% smaller, 228K gates 4.7K (versus 65.5K) 66% fewer bugs 3 major alternatives explored without affecting verification Mieszko Lis, Joe Stoy, Scott Winterble, Brad Sheldon 23
Page 1 and 2: Bluespec: Why chip design can’t b
Page 3 and 4: Pressing problems of chip design Pr
Page 5 and 6: Bluespec A Gap in Chip Design Desig
Page 7 and 8: Bluespec & SystemVerilog high (good
Page 9 and 10: Bluespec: State and Rules organized
Page 11 and 12: GCD in Bluespec module mkGCD (GCD);
Page 13 and 14: Generated Verilog RTL: GCD module m
Page 15 and 16: pc Processor Pipelines and FIFOs fe
Page 17 and 18: Rules for Add implicit checks: bu n
Page 19 and 20: Fetch & Decode Rule: corrected pc C
Page 21: Modular organization pc iMem RFile
Page 25 and 26: Design Problem 64 Items: Index of I
Page 27 and 28: Some advanced features Connectables
Page 29 and 30: MIT work, 1997-2000 TRAC compiler (
Page 31 and 32: Contributors MIT Arvind Dan Rosen
Page 33 and 34: Extras 33
Page 35 and 36: Synthesis from Bluespec 35
Page 37 and 38: Scheduling and control logic Module
Page 39 and 40: Combining State Updates: strawman
Page 41 and 42: Miscellaneous slides 41
Page 43 and 44: Technology validation @ Sandburst M
Page 45: Key concept: “Push” interface,

Bluespec: Why chip design can't be left EE's - MIT

Create successful ePaper yourself

Delete template?

Save as template?