Bluespec: Why chip design can't be left EE's - MIT
Bluespec: Why chip design can't be left EE's - MIT
Bluespec: Why chip design can't be left EE's - MIT
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<strong>Bluespec</strong> & SystemVerilog<br />
high<br />
(good for<br />
modeling, arch.<br />
exploration)<br />
Language Level<br />
low<br />
SystemC<br />
(sim)<br />
low<br />
(ok for simulation)<br />
SystemC<br />
(synth)<br />
Synthesis Quality<br />
<strong>Bluespec</strong><br />
&<br />
System Verilog<br />
VHDL/<br />
Verilog<br />
high<br />
7
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