AN-9044 - Fairchild Semiconductor

6. Interface Circuit
6.1 Input/Output Signal Connection
Mini DIP (SPM3) Application Note (2012-07-09)
Figure 6.1 shows the I/O interface circuit between the CPU and Mini DIP SPM. Because the Mini DIP
SPM input logic is active-high and there are built-in pull-down resistors, external pull-up resistors are not
needed. VFO output is open collector configured. This signal should be pulled up to the positive side of the 5V
external logic power supply by a resistor of approximate 4.7k.
CPU
1nF
100
R = PF
4.7k
C = PF
1nF
5V-Line
Figure 6.1 Recommended CPU I/O Interface Circuit
Table 6.1 Maximum ratings of input and FO pins
© 2008 FAIRCHILD SEMICONDUCTOR - Smart Power Module
24
, ,
IN (UH) IN (VH) IN (WH)
, ,
IN (UL) IN (VL) IN (WL)
V FO
COM
SPM
Item Symbol Condition Rating Unit
Control Supply Voltage VCC
Input Signal Voltage VIN
Applied between
VCC(H) – COM, VCC(L) – COM
Applied between
IN(UH), IN(VH), IN(WH) – COM
IN(UL), IN(VL), IN(WL) – COM
20 V
-0.3 ~ 17 V
Fault Output Supply Voltage VFO Applied between VFO – COM -0.3 ~ VCC+0.3 V
The input and fault output maximum rating voltages are shown in Table 6.1. Since the fault output is
open collector configured, it’s rating is VCC+0.3V, 15V supply interface is possible. However, it is
recommended that the fault output be configured with the 5V logic supply, which is the same as the input
signals. It is also recommended that the by-pass capacitors be placed at both the CPU and Mini DIP SPM
ends of the VFO, signal line as close as possible to each device. The RC coupling at each input (parts shown