Table of Contents Section 1 – New and Featured Products
Table of Contents Section 1 – New and Featured Products
Table of Contents Section 1 – New and Featured Products
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Data Conversion <strong>Products</strong><br />
®<br />
X79000 Flex DAC Family 12 Bit DAC <strong>and</strong> Memory with Selectable Voltage Reference<br />
Product Highlights<br />
• 12-bit resolution DAC<br />
• Selectable full scale <strong>and</strong> zero scale voltages<br />
• 56 Bytes <strong>of</strong> general purpose EEPROM<br />
Key Features<br />
• Monotonic Design<br />
• 5V operation<br />
• Integrated voltage reference option<br />
• Voltage reference input (1.21V) option<br />
• Optional external full scale <strong>and</strong> zero scale references<br />
• SPI interface, 5MHz<br />
• Programmable, non-volatile DAC initial value register<br />
• Optional Up/Down interface<br />
• Up to 6 slave address pins<br />
• Asynchronous clear pin <strong>and</strong> control bit<br />
Benefits<br />
• Programmable V H <strong>and</strong> V L scale values allows the flexibility<br />
to determine the LSB step size.<br />
• Multiple ordering options allow multi-environment applications<br />
• Optional Up/Down interface allows three different LSB<br />
magnitude step adjustments.<br />
• Optional on chip voltage reference eliminates the need<br />
for external referencing.<br />
• Non-volatile memory allows power up recall <strong>and</strong> ready output.<br />
Description<br />
The 79000 is a family <strong>of</strong> Single Channel Digital-to-Analog<br />
Converters with integrated voltage reference, configurable output<br />
buffer, general purpose EEPROM <strong>and</strong> a programmable full<br />
scale <strong>and</strong> zero <strong>of</strong>fset amplifier.<br />
The X79000 series implements a SPI serial bus interface with<br />
slave address identification allowing up to 32 devices on<br />
some options. The full scale <strong>and</strong> zero scale references <strong>and</strong> the<br />
DAC initial value register can be set via the SPI Bus interface.<br />
Optional pins are provided for push-pot style interface<br />
allowing for increment <strong>and</strong> decrement <strong>of</strong> the DAC register in<br />
modulo-2 n-th steps.<br />
A Power On Recall circuit is implemented to keep the DAC<br />
output at high impedance on power up <strong>and</strong> to load an initial<br />
user defined value from non-volatile memory. A power up<br />
ready signal is provided to inform system for operations.<br />
Additional non-volatile memory (56 Bytes) for general purpose<br />
is provided for curve-fit pr<strong>of</strong>ile setting, signal conditioning<br />
parameters, or device <strong>and</strong> system identification.<br />
Pin Configuration<br />
See Datasheet<br />
See Product Family Tree<br />
on page 2-16<br />
<strong>New</strong> & <strong>Featured</strong> <strong>Products</strong><br />
Block Diagram<br />
VH<br />
VL<br />
V OUT<br />
V Ref<br />
Voltage<br />
Reference<br />
Variable Gain<br />
& Level Shift<br />
Variable Gain<br />
& Level Shift<br />
DAC<br />
Core<br />
CE<br />
VBUF<br />
RDY<br />
Power Up<br />
Logic<br />
VFB<br />
DAC Register<br />
CLR<br />
A[5:0]<br />
SCK<br />
SO<br />
SI<br />
CS<br />
Serial<br />
Interface<br />
<strong>and</strong><br />
Control<br />
Logic<br />
General<br />
Purpose<br />
EEPROM<br />
DAC Shift<br />
Register<br />
DAC Initial<br />
Value Register<br />
UP<br />
DOWN<br />
V CC<br />
V SS<br />
www.xicor.com<br />
1<strong>–</strong>69
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