20 Section 2: <strong>CDF</strong> Hardware 2.2.2 D<strong>at</strong>a Acquisition for the Silicon Vertex Detector (SVX) (Prof. Huth, Dr. Maksimovic, Mr. Bailey & Ms. Spiropulu) <strong>The</strong> <strong>Harvard</strong> group has made a long standing eort in SVX d<strong>at</strong>a acquisition, concentr<strong>at</strong>ed on the Silicon Readout Controller (SRC). <strong>The</strong> most recent accomplishments of Huth, Maksimovic, and Bailey, working closely with engineer N<strong>at</strong>han Felt, are described below. Preceding this was the ground-breaking work on the widely used Silicon Test Acquisition and Readout (STAR) system and SVXIII chip by Spiropulu, Colin Gay (now <strong>at</strong> Yale), Raimund Strohmer (now <strong>at</strong> MPI), and engineer John Oliver, which is described next. Overview: Developments from 1993 through 1996 In 1992, a silicon vertex detector was added to <strong>CDF</strong>. It was used to detect secondary vertices from heavy avor weak decays - an excellent tool for b-tags in top physics and for B-physics. Due to radi<strong>at</strong>ion damage in 1993, <strong>CDF</strong> replaced this detector with SVX 0 which uses AC-coupled detectors and a radi<strong>at</strong>ion-hard readout chip. Already in 1993 <strong>CDF</strong> started working on the design of the silicon detector for Run II: the SVXII project. <strong>The</strong> challenge of this project is the \dual ported" pipeline th<strong>at</strong> stores the d<strong>at</strong>a during the form<strong>at</strong>ion of the Level 1 trigger. <strong>The</strong> SVXII project uses the SVXIII chip which supports simultaneous digitiz<strong>at</strong>ion and readout of d<strong>at</strong>a while additional analog d<strong>at</strong>a is entering the pipeline. <strong>The</strong> SVXIII chip was jointly designed by <strong>Fermilab</strong> and LBL. <strong>The</strong> <strong>Harvard</strong> group took responsibility for the design, prototyping, construction, and support of one of the major components of the D<strong>at</strong>a Acquisition stream, namely, the Silicon Readout Controller (SRC). A schem<strong>at</strong>ic of the SVXII DAQ functionality isshown in Fig 12. Long before the nal DAQ system was ready, the SVXII group needed to be able to read out detectors with a chip as close as possible to the nal version (SVXII, SVXIIb). Studies of signal-to-noise r<strong>at</strong>io before and after the silicon suered radi<strong>at</strong>ion damage were required, as well as benchmark measurements of resolution, etc. <strong>The</strong> initial team consisted of Huth (PI) John Oliver (engineer), Gay, Spiropulu and Harlan Robins (undergradu<strong>at</strong>e student). <strong>The</strong> prototype card th<strong>at</strong> we designed and built was called the Silicon Test Acquisition and Readout module (STAR). By the summer of 1996 the <strong>Harvard</strong> group provided seven prototype STAR modules th<strong>at</strong> armed l<strong>at</strong>er test stand facilities all over the world (Lab D <strong>at</strong> <strong>Fermilab</strong>, Pisa, New Mexico, Pittsburgh, KEK, to mention a few; they are still being used with gre<strong>at</strong> success. As the
Section 2: DAQ for the Silicon Vertex Detector 21 <strong>The</strong> SVXII DAQ To Level 3 Trigger <strong>CDF</strong> Clock VME Readout Buffers CMD STAT Silicon Readout Controller CMD STAT Trigger Supervisor To Level 2 Trigger DATA 4 Lines @ 132.5 MB/sec each CMD Fiber Interface Boards STAT CMD DATA 10 Lines @ 53 MB/sec each SVXII Detector Figure 12: Schem<strong>at</strong>ics of the SVX II d<strong>at</strong>a acquisition system.