2 The CDF Experiment at Fermilab Contents - Harvard University ...

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24 Section 2: CDF Hardware FIBs also became available at the same time, and we were able to check the communication protocol between the SRC and the production versions of these boards. As this text is being written, the pilot FIB Fanout (with which the SRC interacts directly) is not yet released, however the preliminary tests showed that the SRC and the FIB Fanout can synchronize the optical link and the SRC can pass commands to the FIB Fanout which then fans them out to FIBs in its crate. In early 1999, few other SRCs have been delivered to Fermilab, to control more sophisticated tests of the other SVX DAQ boards, SVXIII chips, hybrids and port cards. The SRC was rst employed in testing the pilot VRBs in terms of the return error messages that the VRBs pass to the SRC (via VRB Fanout module), which counts them, logs them, and, if necessary, acts upon them. In addition, the VRBs had to pass the so-called \high-speed test", in which ve FIBs are generating fake data, and send them via 50 optical links of production-type length to ten VRBs. VRBs are operating in a mode where they check data consistency and report the errors to the SRC, which counts them. The test is completely driven by the SRC, and the role of software was reduced to telling the SRC to start and stop, and to periodically query SRC's error counters. The test ran at the speed of 4 Gb/s (equivalent to lling up a typical hard-drive in one and a half seconds!), and transferred about 10 16 bytes in just a few days. CDF signed o on the VRB production order, and the SVX group plans on using this test as a model for massive testing of large number of production VRBs. The high-speed test required nalizing the baseline SRC rmware { mainly the logic that handles the error condition in the SVX DAQ, which, in turn, necessitated nalizing the VRB rmware as well. In addition, the specics of the high-speed test required other small modications of the SRC rmware. This illustrates a crucial role that the SRC plays in the testing and commissioning of the SVX DAQ system: its versatility allows for quickly adapting the existing testing paradigms to new needs, as well as designing new ones, with minimal or no modications to the rmware. At the time of writing this report, our focus is on facilitating the testing of various aspect of the operations of SVXIII chips, Intermediate Silicon Layer (ISL) hybrids and compact port cards, e.g., performing gain scans and investigating the noise during digitization and readout while the chip operates in the dead-timeless mode.
Section 2: DAQ for the Silicon Vertex Detector 25 Our Involvement in SVX Software In the Spring of 1997, the rst version of the SVX online software was written at Harvard, by Gay, Spiropulu and Novak. Although it began as the control software for the SRC, due to its exibility and clarity it was soon accepted by the rest of the SVX DAQ group, and then as the core of the CDF-wide protocol for controlling the boards in VME crates. Motivated by the need for testing the SRC at Harvard { in absence of any other SVX DAQ boards { the Harvard group began utilizing General System Test Modules (GSTMs), developed by Fermilab's ESE group. Each GSTM is a generic board with several FIFOs and ports for several types of daughter cards { each emulating a type of connection { that can be attached to the GSTM. In this way a GSTM, adequately controlled by software, can emulate any part of the SVX DAQ system. The low-level GSTM code has been written by Bailey and Maksimovic. A high-level test-stand framework was proposed by Bailey and Maksimovic, was implemented by other members of the SVX DAQ software team, and was extensively used to test VRBs and FIBs using code written by Maksimovic that lets a GSTM emulate a FIB or a VRB. The GSTMs are currently being employed in testing the Hit Finder board of the Secondary Vertex Tracker system (SVT). The SRC software was improved and is maintained mostly by Bailey, who also coded various software tests appropriate for a stand-alone SRC test-stand (such is the one at Harvard). Both Bailey and Maksimovic wrote tests that probe the functionality of the SRC in the environment of the SVX DAQ (such is the one at Fermilab) { tests that involve all elements of the system from the SVXIII chip up, and the ways they interact with the SRC. Future Plans At this point the basic functionality of the SRC has been tested and the majority of the work is in the context of its integration with the rest of the system. This involves ne tuning existing features, performing stress tests of its capabilities, and occasionally adding new features to accommodate a specic test of the complete system. We are also writing documentation for the testing and maintenance of the SRC to facilitate any trouble shooting or repairs that may need to be done in future years when we are not working on the SRC on a daily basis. In the next year Maksimovic and Bailey will be applying their experience with the SVX- DAQ system to aid in the construction and testing of the SVXII detector and will be involved
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Page 3 and 4: Section 2: CDF 3 of Run I data. Rec
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Page 36 and 37: 36 Section 2: CDF 2.3 Run I Physics
Page 38 and 39: 38 Section 2: CDF Physics Analysis
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Section 2: CDF 97 multijet trigger
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Section 2: CDF 99 The Jet Pseudora
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Section 2: CDF 101 while the proble
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Section 2: CDF 103 Talks at Confere
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Section 2: CDF 105 References [1] T
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