2 The CDF Experiment at Fermilab Contents - Harvard University ...
2 The CDF Experiment at Fermilab Contents - Harvard University ...
2 The CDF Experiment at Fermilab Contents - Harvard University ...
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Section 2: DAQ for the Silicon Vertex Detector 23<br />
passes them on to the FIBs its cr<strong>at</strong>e, and also collects the errors from the FIBs and<br />
passes them on back to the SRC. On the SRC end, all logic th<strong>at</strong> deals with four FIB<br />
Fanouts is isol<strong>at</strong>ed into the SRC Transition Module, so, as far as the SRC is concerned,<br />
there is only one FIB Fanout.<br />
Error logging: the production SRC collects the error signals from VRB Fanouts and<br />
FIB Fanouts, counts them and logs them.<br />
Error handling: as the controller of the SVX DAQ system, the SRC is in charge of<br />
how the system must respond to errors, both f<strong>at</strong>al and non-f<strong>at</strong>al, following the so-called<br />
\Halt-Recover-Run" sequence. During the commissioning of the DAQ and the SVX II<br />
detector, most errors will be f<strong>at</strong>al and we will investig<strong>at</strong>e them individually. But once<br />
the d<strong>at</strong>a taking commences, non-f<strong>at</strong>al errors will be logged, and f<strong>at</strong>al errors will be<br />
handled in `auto-recover' mode. Here the interaction between the SRC and the Trigger<br />
Supervisor is crucial, and it depends on whether the error is caused by the SVX system<br />
or not, since in the former case it must take corrective action.<br />
<strong>The</strong> necessary modic<strong>at</strong>ions to the SRC schem<strong>at</strong>ics were mostly made by Felt and postdoc<br />
Petar Maksimovic in the spring of 1998, along with the design of the SRC Transition<br />
Module. <strong>The</strong> SRC and the SRC Transition Module printed circuit boards have been laid<br />
out by Felt. <strong>The</strong> rst production SRC printed circuit boards were delivered in September<br />
1998. One SRC was stued <strong>at</strong> <strong>Harvard</strong> and tested, block by block, by Felt, Maksimovic,<br />
and gradu<strong>at</strong>e student Stephen Bailey, who began spending a signicant portion of his time<br />
on the hardware side of the project. <strong>The</strong> majority of the SRC logic is implemented with<br />
Xilinx Field Programmable G<strong>at</strong>e Arrays (FPGAs) which allows changes and new fe<strong>at</strong>ures<br />
to be added even after the nal hardware has been assembled.<br />
<strong>The</strong> communic<strong>at</strong>ion between SRC and Trigger Supervisor (TS) was partially tested in<br />
November. <strong>The</strong> rst production SRC was brought to <strong>Fermilab</strong> in November { the rst<br />
production board in the SVX DAQ system { and the testing with the nal prototypes of<br />
other SVX boards (FIB Fanout, FIB, VRB Fanout and VRB) began in earnest. After minor<br />
tuning, in early December we were able to read out the SVXIII chip using the SVX DAQ<br />
driven by the new SRC.<br />
After th<strong>at</strong>, other eight SRCs were submitted for assembly, while the SRC transition<br />
modules were stued <strong>at</strong> <strong>Harvard</strong>. Several pairs of SRCs and their transition modules were<br />
delivered to <strong>Fermilab</strong> in January 1999. <strong>The</strong> pilot (\pre-production") versions of VRBs and