ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices

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ADF4251 0 –5 –120 –130 V DD = 3V V P = 3V AMPLITUDE – dBm –10 –15 –20 –25 PRESCALER = 4/5 PRESCALER = 8/9 PHASE NOISE – dB/Hz –140 –150 –160 –30 –170 –35 0 1 2 3 4 5 6 FREQUENCY –GHz TPC 19. RF Input Sensitivity –180 10k 100k 1M 10M PHASE DETECTOR FREQUENCY – Hz TPC 22. Phase Noise (Referred to CP Output) vs. PFD Frequency, IF Side 0 5 V DD = 3V V P 2 = 3V 6 4 IF INPUT POWER – dBm 10 15 20 25 30 35 I CP – mA 2 0 –2 –4 V DD = 3V V P 1 = 5.5V 40 –0.4 0.1 0.6 1.1 1.6 IF INPUT FREQUENCY – GHz TPC 20. IF Input Sensitivity –6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CP – V TPC 23. RF Charge Pump Output Characteristics –120 –130 V DD = 3V V P = 5V 6 4 PHASE NOISE – dB/Hz –140 –150 –160 I CP – mA 2 0 –2 V DD = 3V V P 2 = 3V –170 –4 –180 10k 100k 1M 10M PHASE DETECTOR FREQUENCY – Hz –6 0 0.5 1.0 1.5 2.0 2.5 3.0 V CP – V TPC 21. Phase Noise (Referred to CP Output) vs. PFD Frequency, RF Side TPC 24. IF Charge Pump Output Characteristics –10– REV. 0
ADF4251 CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 3. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down. REF IN = the reference input frequency, D = RF REF IN Doubler Bit, R = the preset divide ratio of the binary 4-bit programmable reference counter (1 to 15), INT = the preset divide ratio of the binary 8-bit counter (31 to 255), MOD = the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095), and FRAC = the preset fractional ratio of the binary 12-bit programmable FRAC counter (0 to MOD). POWER-DOWN CONTROL RF N DIVIDER N = INT + FRAC/MOD REF IN NC NC SW2 SW1 SW3 NO 100k BUFFER XOEB TO R COUNTER REF OUT FROM RF INPUT STAGE N-COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR TO PFD NC = NORMALLY CLOSED NO = NORMALLY OPEN INT REG MOD REG FRAC VALUE Figure 3. Reference Input Stage RF and IF Input Stage The RF input stage is shown in Figure 4. The IF input stage is the same. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the N counter. RF IN A RF IN B BIAS GENERATOR 2k 1.6V 2k Figure 4. RF Input Stage V DD 1 A GND RF INT Divider The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 255 are allowed. INT, FRAC, MOD, and R Relationship The INT, FRAC, and MOD values, in conjunction with the RF R counter, make it possible to generate output frequencies that are spaced by fractions of the RF phase frequency detector (PFD). The equation for the RF VCO frequency (RF OUT ) is Ê RF F INT FRAC ˆ OUT = PFD ¥ Á + Ë MOD ˜ (1) ¯ where RF OUT is the output frequency of external voltage controlled oscillator (VCO). F PFD = REF ¥ IN ( ) 1 + D R (2) Figure 5. N Counter RF R Counter The 4-bit RF R counter allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the RF PFD. Division ratios from 1 to 15 are allowed. IF R Counter The 15-bit IF R counter allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the IF PFD. Division ratios from 1 to 32767 are allowed. IF Prescaler (P/P + 1) The dual modulus IF prescaler (P/P + 1), along with the IF A and B counters, enables the large division ratio, N, to be realized (N = PB + A). Operating at CML levels, it takes the clock from the IF input stage and divides it down to a manageable frequency for the CMOS IF A and CMOS IF B counters. IF A and B Counters The IF A CMOS and IF B CMOS counters combine with the dual modulus IF prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are guaranteed to work when the prescaler output is 150 MHz or less. Pulse Swallow Function The IF A and IF B counters, in conjunction with the dual modulus IF prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. See the Device Programming after Initial Power-Up section for examples. The equation for the IF VCO (IF OUT ) frequency is IF = P ¥ B A F OUT [( ) + ] ¥ PFD (3) where IF OUT = the output frequency of the external voltage controlled oscillator (VCO), P = the preset modulus of the IF dual modulus prescaler, B = the preset divide ratio of the binary 12-bit counter (3 to 4095), and A = the preset divide ratio of the binary 6-bit swallow counter (0 to 63). F PFD is obtained using Equation 2. REV. 0 –11–
Page 1 and 2: Dual Fractional-N/Integer-N Frequen
Page 3 and 4: TIMING CHARACTERISTICS * Limit at T
Page 5 and 6: ADF4251 PIN FUNCTION DESCRIPTIONS M
Page 7 and 8: Typical Performance Characteristics
Page 9: ADF4251 -70 -20 -75 -30 -80 -40 PHA
Page 13 and 14: ADF4251 Table II. Register Summary
Page 15 and 16: ADF4251 Table IV. RF R Divider Regi
Page 17 and 18: ADF4251 Table VI. Master Register M
Page 19 and 20: ADF4251 Table VIII. IF R Divider Re
Page 21 and 22: ADF4251 RF N DIVIDER REGISTER (Addr
Page 23 and 24: ADF4251 When a power-down is activa
Page 25 and 26: IF Side Not In Use If the IF side i
Page 27 and 28: ADF4251 OUTLINE DIMENSIONS 24-Lead

ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices

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