ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices
ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices
ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices
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<strong>ADF4251</strong><br />
PIN FUNCTION DESCRIPTIONS<br />
Mnemonic<br />
CP RF<br />
CP GND 1<br />
RF IN A<br />
RF IN B<br />
A GND 1<br />
MUXOUT<br />
REF IN<br />
CE<br />
D GND<br />
CLK<br />
DATA<br />
LE<br />
R SET<br />
A GND 2<br />
IF IN B<br />
IF IN A<br />
DV DD<br />
CP GND 2<br />
CP IF<br />
V P 2<br />
V DD 2<br />
V DD 3<br />
V DD 1<br />
V P 1<br />
Function<br />
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.<br />
RF Charge Pump Ground<br />
Input to the RF Prescaler. This small signal input is normally taken from the VCO.<br />
Complementary Input to the RF Prescaler<br />
<strong>Analog</strong> Ground for the RF Synthesizer<br />
This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference frequency<br />
to be accessed externally.<br />
Reference Input. This is a CMOS input with a nominal threshold of V DD /2 and an equivalent input resistance of<br />
100 kW. This input can be driven from a TTL or CMOS crystal oscillator.<br />
Chip Enable. A Logic Low on this bit powers down the device and puts the charge pump outputs into three-state.<br />
A Logic High on this pin powers up the device, depending on the status of the software power-down bits.<br />
Digital Ground for the <strong>Fractional</strong> Interpolator<br />
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the<br />
shift register on the CLK rising edge. This input is a high impedance CMOS input.<br />
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a<br />
high impedance CMOS input.<br />
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the<br />
seven latches, the latch being selected using the control bits.<br />
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship<br />
between I CP and R SET is:<br />
ICP MIN = 1.<br />
6875<br />
RSET<br />
Therefore, with R SET = 2.7 kW, I CP MIN = 0.625 mA.<br />
Ground for the IF Synthesizer<br />
Complementary Input to the IF Prescaler<br />
Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.<br />
Positive Power Supply for the <strong>Fractional</strong> Interpolator Section. Decoupling capacitors to the ground plane should<br />
be placed as close as possible to this pin. DV DD must have the same voltage as V DD 1, V DD 2, and V DD 3.<br />
IF Charge Pump Ground<br />
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.<br />
IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible<br />
to this pin. This voltage should be greater than or equal to V DD 2.<br />
Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as<br />
possible to this pin. V DD 2 has a value 3 V ± 10%. V DD 2 must have the same voltage as V DD 1, V DD 3, and DV DD .<br />
Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close<br />
as possible to this pin. V DD 3 has a value 3 V ± 10%. V DD 3 must have the same voltage as V DD 1, V DD 2, and DV DD .<br />
Positive Power Supply for the RF <strong>Analog</strong> Section. Decoupling capacitors to the ground plane should be placed as close<br />
as possible to this pin. V DD 1 has a value 3 V ± 10%. V DD 1 must have the same voltage as V DD 2, V DD 3, and DV DD .<br />
RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible<br />
to this pin. This voltage should be greater than or equal to V DD 1.<br />
REV. 0<br />
–5–