ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices

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<strong>ADF4251</strong> Table V. RF Control Register Map NOISE AND SPUR SETTING 3 RESERVED NOISE AND SPUR SETTING 2 RF CP CURRENT SETTING RESERVED RF PD POLARITY NOISE AND SPUR SETTING 1 RF POWER- DOWN RF CP THREE- STATE RF COUNTER RESET CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N3 T3 T2 T1 N2 CP2 CP1 0 P8 N1 P6 P5 P4 C3 (0) C2 (1) C1 (0) THESE BITS SHOULD EACH BE SET TO 0 FOR NORMAL OPERATION P4 RF COUNTER RESET 0 DISABLED 1 ENABLED N3 N2 N1 NOISE AND SPUR SETTING 0 0 0 LOWEST SPUR 0 0 1 LOW NOISE AND SPUR 1 1 1 LOWEST NOISE P5 RF CP THREE-STATE 0 DISABLED 1 THREE-STATE I CP (mA) CP2 CP1 1.5k 2.7k 5.6k 0 0 1.125 0.625 0.301 0 1 3.375 1.875 0.904 1 0 5.625 3.125 1.506 1 1 7.7875 4.375 2.109 P6 RF POWER-DOWN 0 DISABLED 1 ENABLED P8 RF PD POLARITY 0 NEGATIVE 1 POSITIVE –16– REV. 0
<strong>ADF4251</strong> Table VI. Master Register Map MUXOUT RESERVED POWER- DOWN CP THREE- STATE COUNTER RESET CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M4 M3 M2 M1 P11 P10 P9 C3 (0) C2 (1) C1 (1) M4 M3 M2 M1 MUXOUT P9 COUNTER RESET 0 0 0 0 LOGIC LOW 0 0 0 1 IF ANALOG LOCK DETECT 0 0 1 0 IF R DIVIDER OUTPUT 0 0 1 1 IF N DIVIDER OUTPUT 0 1 0 0 RF ANALOG LOCK DETECT 0 1 0 1 RF/IF ANALOG LOCK DETECT 0 1 1 0 IF DIGITAL LOCK DETECT 0 1 1 1 LOGIC HIGH 1 0 0 0 RF R DIVIDER OUTPUT 1 0 0 1 RF N DIVIDER OUTPUT 1 0 1 0 THREE-STATE OUTPUT 1 0 1 1 LOGIC LOW 1 1 0 0 RF DIGITAL LOCK DETECT 1 1 0 1 RF/IF DIGITAL LOCK DETECT 1 1 1 0 LOGIC HIGH 1 1 1 1 LOGIC LOW P12 P11 0 1 P10 0 1 RESERVED 0 1 POWER-DOWN DISABLED ENABLED DISABLED ENABLED CP THREE-STATE DISABLED THREE-STATE 0 THIS BIT SHOULD BE SET TO “0” FOR NORMAL OPERATION. REV. 0 –17–
Page 1 and 2: Dual Fractional-N/Integer-N Frequen
Page 3 and 4: TIMING CHARACTERISTICS * Limit at T
Page 5 and 6: ADF4251 PIN FUNCTION DESCRIPTIONS M
Page 7 and 8: Typical Performance Characteristics
Page 9 and 10: ADF4251 -70 -20 -75 -30 -80 -40 PHA
Page 11 and 12: ADF4251 CIRCUIT DESCRIPTION Referen
Page 13 and 14: ADF4251 Table II. Register Summary
Page 15: ADF4251 Table IV. RF R Divider Regi
Page 19 and 20: ADF4251 Table VIII. IF R Divider Re
Page 21 and 22: ADF4251 RF N DIVIDER REGISTER (Addr
Page 23 and 24: ADF4251 When a power-down is activa
Page 25 and 26: IF Side Not In Use If the IF side i
Page 27 and 28: ADF4251 OUTLINE DIMENSIONS 24-Lead

ADF4251 Dual Fractional-N/Interger-N Frequency ... - Analog Devices

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