Petr SICHO - Helsinki Institute of Physics

New Pixel FE-I4 chip – goals and issues
• IBM 0,13μm CMOS technology
• Increase the chip size
7,6x10,8mm at FE-I3 to 16,2x18,7mm
at FE-I4, active area 74% to 87%
• Cope with high hit rate
• Reduce the pixel size
(50x400 μm to 50x250 μm)
• Reduce power (385 to 240mW)
• Serial data output rate of the chip -
design target value is 160Mb/s
• Radiation hardness does not look as
serious issue (Vt shift seems to be
much lower at 0,13 μm comparing
with 0,25 μm of present FE-I3 chips)
• Before starting with design of full size
FE-I4 (64r x 324c ) following things
have to be taken into account:
• System architecture: including
DCS, ROD and Opto-links
• Testing (from wafer to irradiation
and test beam)
• Sensors design issues
Pixel size 50 x 250 μm 2
Bump pad diameter 12 μm
Input
Normal pixel input capacitance
range*
DC-coupled negative polarity
300-500 fF
Long pixel input capacitance range* 450-700 fF
In-time threshold with 20ns gate 4000 e
Two-hit time resolution 400 ns
DC leakage current tolerance 100 nA
Single channel ENC sigma (400fF) 300 e
Tuned threshold dispersion 100 e
Analog supply current/pixel @400fF 10 μA
Radiation tolerance 200 MRad
Average hit rate 200 MHz/cm 2
Acquisition mode
Data driven with time stamp
Time stamp precision 8 bits
Readout initiation
Max. number of continuous triggers 16
Trigger command
Trigger latency 3.2 μs
Single chip data output rate 160 Mb/s
1/07/2007
IWORID2008, Helsinky 14