PCS - Part 2: Multiprocessor Architectures

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Example: SUN SF15K (2) memory access times (750 MHz UltraSPARC III) same CPU 216 ns same Board 235 ns different Board 375 ns Communication network: 18x18 Crossbar for address, + cache coherency control signals 18x18 Crossbar for data transfer Peter Sobe PCS - Part 2: Multiprocessor Architectures
Shared Memory and Caching Caches are used in order to release network and main memory from frequent data transfer Non–shared data can be kept in caches for a long time without interaction with main memory This improves scalability of the system, but introduces a consistency problem. This problem is solved by cache coherency protocols. Consistency problem: P1 Consistent P2 P1 Inconsistent P2 Write 23, 2500 23: 1000 23: 1000 23: 1000 23: 2500 23: 1000 23: 1000 23: 2500 after "write−back" Peter Sobe PCS - Part 2: Multiprocessor Architectures
Page 1 and 2: PCS - Part 2: Multiprocessor Archit
Page 3 and 4: Multiprocessor Systems Structure: P
Page 5 and 6: Symmetrical Multiprocessors (SMP) S
Page 7 and 8: Distributed Shared Memory (1) Mix c
Page 9: Example: SUN SF15K (1) Sun SF15K: c
Page 13 and 14: Cache Coherency: MESI (1) Motivatio
Page 15 and 16: Cache Coherency: MESI (3) States an
Page 17 and 18: Example: SUN SF15K (3) Within a sys
Page 19 and 20: Example: SUN SF15K (5) Peter Sobe P
Page 21 and 22: Programming Models: Multithreading
Page 23 and 24: Graphic Processing Units (GPU) Usag
Page 25 and 26: Cuda - Programming (1) NVidia - Com
Page 27: Summary Part 2 Multiprocessor syste

PCS - Part 2: Multiprocessor Architectures

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