PCS - Part 2: Multiprocessor Architectures

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Cache Coherency Coherency: Ensures that no old copies of data are used Weaker than consistency, i.e. inconsistencies are allowed but along with keeping track of inconsistencies Protocols: Invalidation: invalidate a copy when another processor is writing on address (snooping), always write-through is necessary MESI: keep track on usage of data, snooping, write-back only when necessary Directory–based Cache Coherency: for systems without shared address bus Peter Sobe PCS - Part 2: Multiprocessor Architectures
Cache Coherency: MESI (1) Motivation for MESI: Allow the Write-back strategy as long no other processor is accessing to the cached address Protocols similar to MESI also exist for DSM system without a shared snooping medium,⇒directory-based caches The term ’MESI’ comes from the 4 states ’M’,’E’,’S’ and ’I’ Peter Sobe PCS - Part 2: Multiprocessor Architectures
Page 1 and 2: PCS - Part 2: Multiprocessor Archit
Page 3 and 4: Multiprocessor Systems Structure: P
Page 5 and 6: Symmetrical Multiprocessors (SMP) S
Page 7 and 8: Distributed Shared Memory (1) Mix c
Page 9 and 10: Example: SUN SF15K (1) Sun SF15K: c
Page 11: Shared Memory and Caching Caches ar
Page 15 and 16: Cache Coherency: MESI (3) States an
Page 17 and 18: Example: SUN SF15K (3) Within a sys
Page 19 and 20: Example: SUN SF15K (5) Peter Sobe P
Page 21 and 22: Programming Models: Multithreading
Page 23 and 24: Graphic Processing Units (GPU) Usag
Page 25 and 26: Cuda - Programming (1) NVidia - Com
Page 27: Summary Part 2 Multiprocessor syste

PCS - Part 2: Multiprocessor Architectures

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