PCS - Part 2: Multiprocessor Architectures

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Distributed Shared Memory (2) Processor-Memory-Units connected to a multiprocessor system Communication network mostly a hierarchic switched network Asymmetric Structure: Different memory access cost, depending on the referred address and the processor that originates the access Non Uniform Memory Access (NUMA, ccNUMA when cache coherent) Peter Sobe PCS - Part 2: Multiprocessor Architectures
Example: SUN SF15K (1) Sun SF15K: ccNUMA-Multiprocessor system, 72 Sun UltraSparc III - 900 Mhz 18 system boards with 4 processors and 4 memory modules each Within system board: UMA/SMP, cache coherency by snooping Across different system boards: Directory-based cache coherency, implemented by SSM agents Peter Sobe PCS - Part 2: Multiprocessor Architectures
Page 1 and 2: PCS - Part 2: Multiprocessor Archit
Page 3 and 4: Multiprocessor Systems Structure: P
Page 5 and 6: Symmetrical Multiprocessors (SMP) S
Page 7: Distributed Shared Memory (1) Mix c
Page 11 and 12: Shared Memory and Caching Caches ar
Page 13 and 14: Cache Coherency: MESI (1) Motivatio
Page 15 and 16: Cache Coherency: MESI (3) States an
Page 17 and 18: Example: SUN SF15K (3) Within a sys
Page 19 and 20: Example: SUN SF15K (5) Peter Sobe P
Page 21 and 22: Programming Models: Multithreading
Page 23 and 24: Graphic Processing Units (GPU) Usag
Page 25 and 26: Cuda - Programming (1) NVidia - Com
Page 27: Summary Part 2 Multiprocessor syste

PCS - Part 2: Multiprocessor Architectures

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