CAEN V767 128 Channel Gen. Purpose MH TDC - Physics

02/07/2003 V767 User's Manual – Rev.4
3.2. INTERRUPTER CAPABILITY
The Mod. V767 houses a RORA-type VME INTERRUPTER which is generated when
the DATA READY is asserted TRUE.
The interrupt responds to 8 bit, 16 bit and 32 bit interrupt acknowledge cycles providing
an 8-bit STATUS/ID on the VME data lines D00..D07 and removes its interrupt request
when DATA READY is asserted FALSE (see § 3.2.4).
3.2.1. INTERRUPT STATUS/ID
The interrupt STATUS/ID is 8 bit wide, and it is contained in the Interrupt Vector
Register. The register is available at the VME address Base + % 000C.
3.2.2. INTERRUPT LEVEL
The interrupt level corresponds to the value stored in the Interrupt Level Register .
The register is available at the VME address Base + % 000A. A value of 0 in the
Interrupt Level implies that no interrupt is generated.
3.2.3. INTERRUPT GENERATION
The Interrupt Generation occurs on DATA READY condition TRUE. The DATA READY
condition can be programmed via VME (see § 4.9 and 5.7).
3.2.4. INTERRUPT REQUEST RELEASE
The V767 INTERRUPTER removes its Interrupt request when the DATA READY is
asserted FALSE.
In particular:
1) if DATA READY = NOT EMPTY the interrupt request is removed when the
buffer is empty (see also § 4.9.2);
2) if DATA READY = ALM FULL the interrupt request is removed when in
the buffer there are less than n data (n is
programmable; see also § 4.9.3);
3) if DATA READY = EVENT READY the interrupt request is removed when in
the buffer there is no more a complete
event (see also § 4.9.1).
NPO:
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