CAEN V767 128 Channel Gen. Purpose MH TDC - Physics

02/07/2003 V767 User's Manual – Rev.4
3.11. CONTROL REGISTER 1
(Base address + %0010 read/write)
This register allows to perform some general settings of the module.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BLKEND
PROG_RESET
BERR_ENABLE
Fig. 3.10: Control Register 1
BLK_END
data.
PROGRESET
BERR_EN
End of Block bit. Used in Block Transfer mode only.
= 0 The module sends to the CPU all the requested data;
when the Output Buffer is empty it will send not valid
If BERR_VME is enabled, a Bus Error is generated with
the readout of the last word in the Output Buffer.
= 1 The module sends to the CPU all data until the first EOB word
(End of first event); afterwards it will send not valid data.
If BERR_VME is enabled, a Bus Error is generated with
the readout of the EOB word.
Programmable Reset Mode setting bit.
= 0 the front panel RESET acts only on data;
= 1 the front panel RESET acts on all the module,
including the Front End.
Bus Error enable bit. Used in Block Transfer mode only.
(Bits 9 to 15 are meaningless).
= 1 BERR_VME line enabled.
3.12. ADDRESS DECODER REGISTER 32
(Base address + %0012 read/write)
This register contains the A31..A24 bits of the address of the module: it can be set via
VME for a relocation of the Base Address of the module, as described in [6]. The
register content is the following:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A[31:24]
Fig. 3.11: ADER 32 Register
NPO:
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