CAEN V767 128 Channel Gen. Purpose MH TDC - Physics

02/07/2003 V767 User's Manual – Rev.4
The status of the boards according to the bit value is the following:
Board Status FIRST_BOARD bit LAST_BOARD bit
Board disabled in CBLT or MCST chain 0 0
First board in CBLT or MCST chain 1 0
Last board in CBLT or MCST chain 0 1
Active intermediate board in CBLT
or MCST chain (neither first nor last)
1 1
(Bits 2 to 15 are meaningless).
3.17. STATUS REGISTER 2
(Base address + %0048 read only)
This register contains further information on the status of the module buffer and TDC
errors.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUFFER EMPTY
BUFFER FULL
BUFFER ALMOST FULL
GLOBAL TDC ERROR
RESERVED
TDC 0 ERROR
TDC 1 ERROR
TDC 2 ERROR
TDC 3 ERROR
Fig. 3.15: Status Register 2
BUFFER EMPTY:
BUFFER FULL:
Indicates if the Output Buffer is empty.
= 0 Buffer Not Empty.
= 1 Buffer Empty.
Indicates if the Output Buffer is full.
= 0 Buffer Not Full.
= 1 Buffer Full.
BUFF. ALMOST FULL: Indicates if the Output Buffer is almost full. The selection of
the Almost Full status is programmable via OPCODE (see
§ 4.9.5).
= 0 Buffer Not Almost Full.
= 1 Buffer Almost Full.
GLOBAL TDC ERROR: Indicates that at least a TDC chip has an error (See § 4.10.1).
= 0 No TDC chip has an error.
= 1 At least a TDC chip has an error.
TDC 0..3 ERROR:
Indicates that a selected (0..3) TDC chip has an error (See
§ 4.10.1).
NPO:
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