CAEN V767 128 Channel Gen. Purpose MH TDC - Physics

02/07/2003 V767 User's Manual – Rev.4
3.20. CLEAR EVENT COUNTER REGISTER
(Base address + %004E write only)
A VME access (read or write) to this location clears the Event Counter.
3.21. OPCODE HANDSHAKE REGISTER
(Base address + %0050 read only)
The Opcode Handshake Register is used for the Handshake Protocol between the VME
and the microcontroller. It uses only 2 bits: READ OK and WRITE OK.
All read and write operations with the Opcode Register can be performed, respectively,
when the bit RO or WO is set. See § 4 for the usage of this register.
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1
0
WORO
Read OK
Write OK
Fig. 3.18: Opcode Handshake Register
N.B.: because of V767 module's internal delays it is necessary to insert a 10-ms
delay in the software after the check of the RO/WO bit, i.e. before performing the
next R/W operation on the Opcode Register.
3.22. OPCODE REGISTER
(Base address + %0052 read/write)
The Opcode Register is used to send instructions to the microcontroller via 16-bit
OPCODE setup words. The usage of this register is fully described in § 4.
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1
0
COMMAND
OBJECT
Fig. 3.19: Opcode Register
3.23. CLEAR REGISTER
(Base address + %0054 write only)
A VME access (read or write) to this location causes the following:
1. the TDCs are cleared;
2. the output buffer is cleared;
3. the readout controller is reset;
4. the Event counter is set to 0.
The same actions are performed at Power-ON and if the VME signal SYSRES is active.
NPO:
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