Unit – 3 Session - 12 Data Processing Circuits - VTU e-Learning ...
Unit – 3 Session - 12 Data Processing Circuits - VTU e-Learning ...
Unit – 3 Session - 12 Data Processing Circuits - VTU e-Learning ...
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10CS 33 LOGIC DESIGN<br />
UNIT <strong>–</strong> 3 <strong>Data</strong> <strong>Processing</strong> <strong>Circuits</strong><br />
BCD Input<br />
Outputs<br />
A B C D a b c d e f g<br />
0 0 0 0 1 1 1 1 1 1 0<br />
0 0 0 1 0 1 1 0 0 0 0<br />
0 0 1 0 1 1 0 1 1 0 1<br />
0 0<br />
0 1<br />
0 1<br />
0 1<br />
0 1<br />
1 0<br />
1 0<br />
1 1 1 1 1 1 0 0 1<br />
0 0 0 1 1 0 0 1 1<br />
0 1 1 0 1 1 0 1 1<br />
1 0 1 0 1 1 1 1 1<br />
1 1 1 1 1 0 0 0 0<br />
0 0 1 1 1 1 1 1 1<br />
0 1 1 1 1 0 0 1 1<br />
The 7-segment decoder is realized using PLA as shown below:<br />
B. S. Umashankar, BNMIT<br />
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