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SVX4 User's Manual

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FERMILAB-TM-2317-E<br />

Test Results for the <strong>SVX4</strong> Version A/B Chip D∅ Note 4251<br />

Ramp Pedestal Setting Pedestal (CDF mode) Pedestal (D∅ mode)<br />

0 193 193<br />

1 176 176.5<br />

2 160 160<br />

3 143 143<br />

4 127 127<br />

5 111 111<br />

6 94.5 95<br />

7 78 78.5<br />

8 62.5 62.5<br />

9 46 46.5<br />

10 30.5 30.5<br />

11 17 17<br />

12 32 32<br />

13 48 48.5<br />

14 63 63<br />

15 150 157<br />

Table 6 Measured pedestal values as a function of the downloaded values for the Ramp Pedestal<br />

setting. These values were taken with a Ramp Range setting of 0 and a digitization frequency of 50<br />

MHz. All values are in ADC counts.<br />

Pedestal Scan<br />

250<br />

Pedestal (ADC counts)<br />

200<br />

150<br />

100<br />

50<br />

CDF mode (Normal Pol)<br />

CDF mode (Reverse<br />

Pol)<br />

D0 mode (Normal Pol)<br />

D0 mode (Reverse Pol)<br />

0<br />

0 5 10 15 20<br />

Ramp pedestal setting<br />

Figure 18 Graphical representation of the pedestal values for the <strong>SVX4</strong> version B chip. The Ramp<br />

Range value was 0 and the digitization frequency was 50 MHz.<br />

A new feature was added to the <strong>SVX4</strong> version B that allows the user to set the pedestal in<br />

the ramp down direction with different step widths. It is important to note that for ramp<br />

D∅ RunIIb Group Page 18 6/20/2005

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