PIC18F2480/2580/4480/4580 Data Sheet - Microchip

PIC18F2480/2580/4480/4580
FIGURE 1-1:
Table Pointer
PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM
Data Bus
inc/dec logic
21
20
PCLATU PCLATH
8 8
PCU PCH PCL
Program Counter
Data Latch
Data Memory
(.7, 1.5 Kbytes)
Address Latch
12
Data Address
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
8
Instruction Bus
31 Level Stack
STKPTR
Table Latch
ROM Latch
IR
4 12 4
BSR
FSR0
Access
Bank
FSR1
FSR2 12
inc/dec
logic
Address
Decode
PORTB
RB0/INT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1 (2)
OSC2 (2)
T1OSI
T1OSO
MCLR (1)
VDD, VSS
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Instruction
Decode &
Control
State machine
control signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
3
BITOP
8
PRODH PRODL
8
Band Gap
Reference
8 x 8 Multiply
W
8
ALU
8
8
8
8
8
PORTC
PORTE
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR/VPP/RE3 (1)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
ECCP1
MSSP
EUSART
ADC
10-bit
ECAN
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39637A-page 10 Preliminary © 2004 Microchip Technology Inc.