PIC18F2480/2580/4480/4580 Data Sheet - Microchip

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PIC18F2480/2580/4480/4580 NOTES: DS39637A-page 32 Preliminary © 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 3.0 POWER MANAGED MODES PIC18F2480/2580/4480/4580 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power managed modes: • Run modes • Idle modes • Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power managed modes include several power saving features offered on previous PICmicro ® devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PICmicro devices, where all device clocks are stopped. 3.1 Selecting Power Managed Modes Selecting a power managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power managed modes. They are: • the primary clock, as defined by the FOSC3:FOSC0 configuration bits • the secondary clock (the Timer1 oscillator) • the internal oscillator block (for RC modes) 3.1.2 ENTERING POWER MANAGED MODES Switching from one power managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 “Clock Transitions and Status Indicators” and subsequent sections. Entry to the Power Managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. TABLE 3-1: POWER MANAGED MODES OSCCON bits Module Clocking Mode Available Clock and Oscillator Source IDLEN (1) SCS1:SCS0 CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC (2) : This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block (2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block (2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2004 Microchip Technology Inc. Preliminary DS39637A-page 33
Page 1 and 2: PIC18F2480/2580/4480/4580 Data Shee
Page 3 and 4: PIC18F2480/2580/4480/4580 28/40/44-
Page 5 and 6: © 2004 Microchip Technology Inc. P
Page 7 and 8: PIC18F2480/2580/4480/4580 TO OUR VA
Page 9 and 10: PIC18F2480/2580/4480/4580 1.0 DEVIC
Page 11 and 12: PIC18F2480/2580/4480/4580 TABLE 1-1
Page 13 and 14: PIC18F2480/2580/4480/4580 FIGURE 1-
Page 25 and 26: PIC18F2480/2580/4480/4580 2.0 OSCIL
Page 27 and 28: PIC18F2480/2580/4480/4580 2.4 RC Os
Page 29 and 30: PIC18F2480/2580/4480/4580 REGISTER
Page 31 and 32: PIC18F2480/2580/4480/4580 2.7.1 OSC
Page 33: PIC18F2480/2580/4480/4580 2.8 Effec
Page 39 and 40: PIC18F2480/2580/4480/4580 3.3 Sleep
Page 41 and 42: PIC18F2480/2580/4480/4580 3.4.3 RC_
Page 43 and 44: PIC18F2480/2580/4480/4580 4.0 RESET
Page 45 and 46: PIC18F2480/2580/4480/4580 4.2 Maste
Page 47 and 48: PIC18F2480/2580/4480/4580 4.5 Devic
Page 63 and 64: PIC18F2480/2580/4480/4580 5.0 MEMOR
Page 65 and 66: PIC18F2480/2580/4480/4580 5.1.2.2 R
Page 67 and 68: PIC18F2480/2580/4480/4580 5.2 PIC18
Page 69 and 70: PIC18F2480/2580/4480/4580 5.3 Data
Page 73 and 74: PIC18F2480/2580/4480/4580 5.3.4 SPE
Page 85 and 86:
PIC18F2480/2580/4480/4580 TABLE 5-2
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PIC18F2480/2580/4480/4580 TABLE 5-2
Page 89 and 90:
PIC18F2480/2580/4480/4580 TABLE 5-2
Page 91 and 92:
PIC18F2480/2580/4480/4580 5.4 Data
Page 93 and 94:
PIC18F2480/2580/4480/4580 5.4.3.2 F
Page 95 and 96:
PIC18F2480/2580/4480/4580 FIGURE 5-
Page 97 and 98:
PIC18F2480/2580/4480/4580 6.0 FLASH
Page 99 and 100:
PIC18F2480/2580/4480/4580 REGISTER
Page 101 and 102:
PIC18F2480/2580/4480/4580 6.3 Readi
Page 103 and 104:
PIC18F2480/2580/4480/4580 6.5 Writi
Page 105 and 106:
PIC18F2480/2580/4480/4580 EXAMPLE 6
Page 107 and 108:
PIC18F2480/2580/4480/4580 7.0 DATA
Page 109 and 110:
PIC18F2480/2580/4480/4580 7.3 Readi
Page 111 and 112:
PIC18F2480/2580/4480/4580 TABLE 7-1
Page 113 and 114:
PIC18F2480/2580/4480/4580 8.0 8 x 8
Page 115 and 116:
PIC18F2480/2580/4480/4580 9.0 INTER
Page 117 and 118:
PIC18F2480/2580/4480/4580 9.1 INTCO
Page 119 and 120:
PIC18F2480/2580/4480/4580 REGISTER
Page 121 and 122:
PIC18F2480/2580/4480/4580 REGISTER
Page 123 and 124:
PIC18F2480/2580/4480/4580 9.3 PIE R
Page 125 and 126:
PIC18F2480/2580/4480/4580 REGISTER
Page 127 and 128:
PIC18F2480/2580/4480/4580 REGISTER
Page 129 and 130:
PIC18F2480/2580/4480/4580 9.5 RCON
Page 131 and 132:
PIC18F2480/2580/4480/4580 10.0 I/O
Page 133 and 134:
PIC18F2480/2580/4480/4580 TABLE 10-
Page 135 and 136:
PIC18F2480/2580/4480/4580 TABLE 10-
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PIC18F2480/2580/4480/4580 10.3 PORT
Page 139 and 140:
PIC18F2480/2580/4480/4580 TABLE 10-
Page 141 and 142:
PIC18F2480/2580/4480/4580 TABLE 10-
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PIC18F2480/2580/4480/4580 10.5 PORT
Page 145 and 146:
PIC18F2480/2580/4480/4580 TABLE 10-
Page 147 and 148:
PIC18F2480/2580/4480/4580 FIGURE 10
Page 149 and 150:
PIC18F2480/2580/4480/4580 11.0 TIME
Page 151 and 152:
PIC18F2480/2580/4480/4580 11.3 Pres
Page 153 and 154:
PIC18F2480/2580/4480/4580 12.0 TIME
Page 155 and 156:
PIC18F2480/2580/4480/4580 12.2 Time
Page 157 and 158:
PIC18F2480/2580/4480/4580 EXAMPLE 1
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PIC18F2480/2580/4480/4580 13.0 TIME
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PIC18F2480/2580/4480/4580 14.0 TIME
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PIC18F2480/2580/4480/4580 14.2 Time
Page 165 and 166:
PIC18F2480/2580/4480/4580 15.0 CAPT
Page 167 and 168:
PIC18F2480/2580/4480/4580 15.2 Capt
Page 169 and 170:
PIC18F2480/2580/4480/4580 15.3 Comp
Page 171 and 172:
PIC18F2480/2580/4480/4580 15.4 PWM
Page 173 and 174:
PIC18F2480/2580/4480/4580 TABLE 15-
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PIC18F2480/2580/4480/4580 16.0 ENHA
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PIC18F2480/2580/4480/4580 16.4 Enha
Page 179 and 180:
PIC18F2480/2580/4480/4580 FIGURE 16
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PIC18F2480/2580/4480/4580 16.4.5 FU
Page 183 and 184:
PIC18F2480/2580/4480/4580 FIGURE 16
Page 185 and 186:
PIC18F2480/2580/4480/4580 REGISTER
Page 187 and 188:
PIC18F2480/2580/4480/4580 16.4.9 SE
Page 189 and 190:
PIC18F2480/2580/4480/4580 17.0 MAST
Page 191 and 192:
PIC18F2480/2580/4480/4580 REGISTER
Page 193 and 194:
PIC18F2480/2580/4480/4580 17.3.3 EN
Page 195 and 196:
PIC18F2480/2580/4480/4580 17.3.6 SL
Page 197 and 198:
PIC18F2480/2580/4480/4580 17.3.8 OP
Page 199 and 200:
PIC18F2480/2580/4480/4580 REGISTER
Page 201 and 202:
PIC18F2480/2580/4480/4580 REGISTER
Page 203 and 204:
PIC18F2480/2580/4480/4580 17.4.3.2
Page 205 and 206:
PIC18F2480/2580/4480/4580 FIGURE 17
Page 207 and 208:
PIC18F2480/2580/4480/4580 FIGURE 17
Page 209 and 210:
PIC18F2480/2580/4480/4580 17.4.4.5
Page 211 and 212:
PIC18F2480/2580/4480/4580 FIGURE 17
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PIC18F2480/2580/4480/4580 17.4.6 MA
Page 215 and 216:
PIC18F2480/2580/4480/4580 17.4.7 BA
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PIC18F2480/2580/4480/4580 17.4.8 I
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PIC18F2480/2580/4480/4580 17.4.10 I
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PIC18F2480/2580/4480/4580 FIGURE 17
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PIC18F2480/2580/4480/4580 17.4.14 S
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PIC18F2480/2580/4480/4580 FIGURE 17
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PIC18F2480/2580/4480/4580 17.4.17.3
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PIC18F2480/2580/4480/4580 18.0 ENHA
Page 231 and 232:
PIC18F2480/2580/4480/4580 REGISTER
Page 233 and 234:
PIC18F2480/2580/4480/4580 18.1 Baud
Page 235 and 236:
PIC18F2480/2580/4480/4580 TABLE 18-
Page 237 and 238:
PIC18F2480/2580/4480/4580 FIGURE 18
Page 239 and 240:
PIC18F2480/2580/4480/4580 FIGURE 18
Page 241 and 242:
PIC18F2480/2580/4480/4580 FIGURE 18
Page 243 and 244:
PIC18F2480/2580/4480/4580 18.2.5 BR
Page 245 and 246:
PIC18F2480/2580/4480/4580 FIGURE 18
Page 247 and 248:
PIC18F2480/2580/4480/4580 18.4 EUSA
Page 249 and 250:
PIC18F2480/2580/4480/4580 19.0 10-B
Page 251 and 252:
PIC18F2480/2580/4480/4580 REGISTER
Page 253 and 254:
PIC18F2480/2580/4480/4580 The value
Page 255 and 256:
PIC18F2480/2580/4480/4580 19.2 Sele
Page 257 and 258:
PIC18F2480/2580/4480/4580 19.6 A/D
Page 259 and 260:
PIC18F2480/2580/4480/4580 20.0 COMP
Page 261 and 262:
PIC18F2480/2580/4480/4580 20.2 Comp
Page 263 and 264:
PIC18F2480/2580/4480/4580 20.9 Anal
Page 265 and 266:
PIC18F2480/2580/4480/4580 21.0 COMP
Page 267 and 268:
PIC18F2480/2580/4480/4580 FIGURE 21
Page 269 and 270:
PIC18F2480/2580/4480/4580 22.0 HIGH
Page 271 and 272:
PIC18F2480/2580/4480/4580 22.2 HLVD
Page 273 and 274:
PIC18F2480/2580/4480/4580 22.6 Oper
Page 275 and 276:
PIC18F2480/2580/4480/4580 23.0 ECAN
Page 277 and 278:
PIC18F2480/2580/4480/4580 23.2 CAN
Page 279 and 280:
PIC18F2480/2580/4480/4580 REGISTER
Page 281 and 282:
PIC18F2480/2580/4480/4580 EXAMPLE 2
Page 283 and 284:
PIC18F2480/2580/4480/4580 REGISTER
Page 285 and 286:
PIC18F2480/2580/4480/4580 REGISTER
Page 287 and 288:
PIC18F2480/2580/4480/4580 REGISTER
Page 289 and 290:
PIC18F2480/2580/4480/4580 23.2.3 DE
Page 291 and 292:
PIC18F2480/2580/4480/4580 REGISTER
Page 293 and 294:
PIC18F2480/2580/4480/4580 REGISTER
Page 295 and 296:
PIC18F2480/2580/4480/4580 REGISTER
Page 297 and 298:
PIC18F2480/2580/4480/4580 REGISTER
Page 299 and 300:
PIC18F2480/2580/4480/4580 REGISTER
Page 301 and 302:
PIC18F2480/2580/4480/4580 REGISTER
Page 303 and 304:
PIC18F2480/2580/4480/4580 REGISTER
Page 305 and 306:
PIC18F2480/2580/4480/4580 REGISTER
Page 307 and 308:
PIC18F2480/2580/4480/4580 REGISTER
Page 309 and 310:
PIC18F2480/2580/4480/4580 REGISTER
Page 311 and 312:
PIC18F2480/2580/4480/4580 REGISTER
Page 313 and 314:
PIC18F2480/2580/4480/4580 23.2.4 CA
Page 315 and 316:
PIC18F2480/2580/4480/4580 REGISTER
Page 317 and 318:
PIC18F2480/2580/4480/4580 23.2.6 CA
Page 319 and 320:
PIC18F2480/2580/4480/4580 REGISTER
Page 321 and 322:
PIC18F2480/2580/4480/4580 TABLE 23-
Page 323 and 324:
PIC18F2480/2580/4480/4580 TABLE 23-
Page 325 and 326:
PIC18F2480/2580/4480/4580 TABLE 23-
Page 327 and 328:
PIC18F2480/2580/4480/4580 23.3.4 LI
Page 329 and 330:
PIC18F2480/2580/4480/4580 23.5.4 PR
Page 331 and 332:
PIC18F2480/2580/4480/4580 23.7 Mess
Page 333 and 334:
PIC18F2480/2580/4480/4580 In Mode 1
Page 335 and 336:
PIC18F2480/2580/4480/4580 23.9.1 EX
Page 337 and 338:
PIC18F2480/2580/4480/4580 23.9.2 TI
Page 339 and 340:
PIC18F2480/2580/4480/4580 FIGURE 23
Page 341 and 342:
PIC18F2480/2580/4480/4580 The PIC18
Page 343 and 344:
PIC18F2480/2580/4480/4580 23.15.6.1
Page 345 and 346:
PIC18F2480/2580/4480/4580 24.0 SPEC
Page 347 and 348:
PIC18F2480/2580/4480/4580 REGISTER
Page 349 and 350:
PIC18F2480/2580/4480/4580 REGISTER
Page 351 and 352:
PIC18F2480/2580/4480/4580 REGISTER
Page 353 and 354:
PIC18F2480/2580/4480/4580 REGISTER
Page 355 and 356:
PIC18F2480/2580/4480/4580 REGISTER
Page 357 and 358:
PIC18F2480/2580/4480/4580 24.4 Fail
Page 359 and 360:
PIC18F2480/2580/4480/4580 24.5 Prog
Page 361 and 362:
PIC18F2480/2580/4480/4580 FIGURE 24
Page 363 and 364:
PIC18F2480/2580/4480/4580 25.0 INST
Page 365 and 366:
PIC18F2480/2580/4480/4580 FIGURE 25
Page 367 and 368:
PIC18F2480/2580/4480/4580 TABLE 25-
Page 369 and 370:
PIC18F2480/2580/4480/4580 25.1.1 ST
Page 371 and 372:
PIC18F2480/2580/4480/4580 ANDWF AND
Page 373 and 374:
PIC18F2480/2580/4480/4580 BNC Branc
Page 375 and 376:
PIC18F2480/2580/4480/4580 BRA Uncon
Page 377 and 378:
PIC18F2480/2580/4480/4580 BTG Bit T
Page 379 and 380:
PIC18F2480/2580/4480/4580 CLRF Clea
Page 381 and 382:
PIC18F2480/2580/4480/4580 CPFSGT Co
Page 383 and 384:
PIC18F2480/2580/4480/4580 DECFSZ De
Page 385 and 386:
PIC18F2480/2580/4480/4580 INCFSZ In
Page 387 and 388:
PIC18F2480/2580/4480/4580 LFSR Load
Page 389 and 390:
PIC18F2480/2580/4480/4580 MOVLW Mov
Page 391 and 392:
PIC18F2480/2580/4480/4580 NEGF Nega
Page 393 and 394:
PIC18F2480/2580/4480/4580 RCALL Rel
Page 395 and 396:
PIC18F2480/2580/4480/4580 RETURN Re
Page 397 and 398:
PIC18F2480/2580/4480/4580 RRNCF Rot
Page 399 and 400:
PIC18F2480/2580/4480/4580 SUBLW Sub
Page 401 and 402:
PIC18F2480/2580/4480/4580 TBLRD Tab
Page 403 and 404:
PIC18F2480/2580/4480/4580 TSTFSZ Te
Page 405 and 406:
PIC18F2480/2580/4480/4580 25.2 Exte
Page 407 and 408:
PIC18F2480/2580/4480/4580 CALLW Sub
Page 409 and 410:
PIC18F2480/2580/4480/4580 SUBFSR Su
Page 411 and 412:
PIC18F2480/2580/4480/4580 ADDWF ADD
Page 413 and 414:
PIC18F2480/2580/4480/4580 26.0 DEVE
Page 415 and 416:
PIC18F2480/2580/4480/4580 26.9 MPLA
Page 417 and 418:
PIC18F2480/2580/4480/4580 26.20 PIC
Page 419 and 420:
PIC18F2480/2580/4480/4580 27.0 ELEC
Page 421 and 422:
PIC18F2480/2580/4480/4580 27.1 DC C
Page 423 and 424:
PIC18F2480/2580/4480/4580 27.2 DC C
Page 425 and 426:
PIC18F2480/2580/4480/4580 27.2 DC C
Page 427 and 428:
PIC18F2480/2580/4480/4580 27.2 DC C
Page 429 and 430:
PIC18F2480/2580/4480/4580 27.3 DC C
Page 431 and 432:
PIC18F2480/2580/4480/4580 TABLE 27-
Page 433 and 434:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 435 and 436:
PIC18F2480/2580/4480/4580 27.4.2 TI
Page 437 and 438:
PIC18F2480/2580/4480/4580 TABLE 27-
Page 439 and 440:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 441 and 442:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 443 and 444:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 445 and 446:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 447 and 448:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 449 and 450:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 451 and 452:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 453 and 454:
PIC18F2480/2580/4480/4580 FIGURE 27
Page 455 and 456:
PIC18F2480/2580/4480/4580 28.0 DC A
Page 457 and 458:
PIC18F2480/2580/4480/4580 29.0 PACK
Page 459 and 460:
PIC18F2480/2580/4480/4580 29.2 Pack
Page 461 and 462:
PIC18F2480/2580/4480/4580 28-Lead P
Page 463 and 464:
PIC18F2480/2580/4480/4580 44-Lead P
Page 465 and 466:
PIC18F2480/2580/4480/4580 APPENDIX
Page 467 and 468:
PIC18F2480/2580/4480/4580 APPENDIX
Page 469 and 470:
PIC18F2480/2580/4480/4580 INDEX A A
Page 471 and 472:
PIC18F2480/2580/4480/4580 Data Memo
Page 473 and 474:
PIC18F2480/2580/4480/4580 Master Mo
Page 475 and 476:
PIC18F2480/2580/4480/4580 RA1/AN1 .
Page 477 and 478:
PIC18F2480/2580/4480/4580 EECON1 (D
Page 479 and 480:
PIC18F2480/2580/4480/4580 I 2 C Bus
Page 481 and 482:
PIC18F2480/2580/4480/4580 ON-LINE S
Page 483 and 484:
PIC18F2480/2580/4480/4580 PIC18F248
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PIC18F2480/2580/4480/4580 Data Sheet - Microchip

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