DUAL-PORT MEMORY BLOCK DIAGRAM DUALL-PORT RAM CELL

DUAL-PORT MEMORY
BLOCK DIAGRAM
CPU
OR
I/O
DEVICE
"L"
DATA
ADDRESS
R/W
L
DATA
I/O
L
ADDRESS
DECODER
DUAL/PORT
RAM
MEMORY
CELLS
R
DATA
I/O
R
ADDRESS
DECODER
DATA
ADDRESS
R/W
CPU
OR
I/O
DEVICE
"R"
BUSY,
INTERRUPT,
SEMAPHORE
CONTROL LOGIC
BUSY,
INTERRUPT,
SEMAPHORE
DUALL-PORT RAM CELL
L SIDE WRITE DRIVERS
R SIDE WRITE DRIVERS
L SELECT
(DECODED
ADDRESS)
L WRITE
WR
1
WR
0
WR
1
WR
0
R SELECT
(DECODED
ADDRESS)
R WRITE
L DATA BIT LINE
RD
RD
R DATA BIT LINE
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
1

DUALL-PORT RAM CELL - Read
L SIDE WRITE DRIVERS
R SIDE WRITE DRIVERS
L SELECT
(DECODED
ADDRESS)
L WRITE
WR
1
WR
0
WR
1
WR
0
R SELECT
(DECODED
ADDRESS)
R WRITE
L DATA BIT LINE
RD
RD
R DATA BIT LINE
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
DUALL-PORT RAM CELL - Write
L SIDE WRITE DRIVERS
R SIDE WRITE DRIVERS
L SELECT
(DECODED
ADDRESS)
L WRITE
WR
1
WR
0
WR
1
WR
0
R SELECT
(DECODED
ADDRESS)
R WRITE
L DATA BIT LINE
RD
RD
R DATA BIT LINE
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
2

DUALL-PORT RAM
Interrupt Logic
L SIDE WRITE
INTERRUPT
TO R SIDE
L SIDE
ADDRESS
ADDRESS
= 3FF
ADDRESS
= 3FE
R SIDE READ
L SIDE READ
ADDRESS
= 3FF
ADDRESS
= 3FE
R SIDE
ADDRESS
INTERRUPT
TO L SIDE
R SIDE WRITE
DUUALL-PORT RAM
Busy Logic
ADDRESS (L)
DELAY BUFFER
DELAY BUFFER
ADDRESS (R)
ADDRESS
EQUAL
COMPARATOR
ADDRESS
EQUAL
COMPARATOR
CE (L)
CE (R)
BUSY (L)
L
R
BUSY (R)
WRITE INHIBIT (L)
A
B
WRITE INHIBIT (R)
3

DUAL-PORT RAM
Semaphore Logic
CPU
OR
I/O
DEVICE
"L"
DATA
ADDRESS
R/W
L
DATA
I/O
L
ADDRESS
DECODER
DUAL/PORT
RAM
MEMORY
CELLS
R
DATA
I/O
R
ADDRESS
DECODER
DATA
ADDRESS
R/W
CPU
OR
I/O
DEVICE
"R"
SEMAPHORE
SELECT
SEMAPHORE
CELLS
SEMAPHORE
SELECT
DUAL-PORT RAM
Semaphore Logic cell
L D-LATCH
R D-LATCH
L REQUEST
D
Q
1 1
Q
D
R REQUEST
L WR SEMAPHORE
E
E
R WR SEMAPHORE
GRANT (L)
SEMAPHORE
ARBITRATION
LATCH
GRANT (R)
4