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Contents RM0016 24.11.18 ADC watchdog control register low (ADC_AWCRL) . . . . . . . . . . . . . . 436 24.12 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 16/449 Doc ID 14587 Rev 8 www.BDTIC.com/ST
RM0016 List of tables List of tables Table 1. Interrupt levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 2. CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3. CFG_GCR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. List of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5. Block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 6. Memory access versus programming method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 7. Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 8. Software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 9. Interrupt enabling/disabling inside an ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10. Vector address map versus software priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 11. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 12. Interrupt register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 13. RST register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 14. Devices with 4 trimming bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 15. Devices with 3 trimming bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 16. CLK interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 17. Peripheral clock gating bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 18. Peripheral clock gating bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 19. CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 20. Low power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 21. I/O port configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 22. Effect of low power modes on GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 23. Recommended and non-recommended configurations for analog input . . . . . . . . . . . . . 109 Table 24. GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 25. Time base calculation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 26. AWU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 27. Beeper register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 28. Watchdog timeout period (LSI clock frequency = 128 kHz) . . . . . . . . . . . . . . . . . . . . . . . 123 Table 29. IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 30. Window watchdog timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 31. Effect of low power modes on WWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 32. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 33. Timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 34. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 35. Glossary of internal timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 36. Explanation of indices‘i’, ‘n’, and ‘x’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 37. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 38. Output control for complementary OCi and OCiN channels with break feature . . . . . . . . 202 Table 39. TIM1 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 40. TIM2 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 41. TIM3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 42. TIM5 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 43. TIM4 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 44. TIM6 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 45. SPI behavior in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Table 46. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Table 47. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 48. I 2 C interface behavior in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Doc ID 14587 Rev 8 17/449 www.BDTIC.com/ST
Page 1 and 2: RM0016 Reference manual STM8S and S
Page 3 and 4: RM0016 Contents 4.5.3 Enabling writ
Page 5 and 6: RM0016 Contents 9.7 Clock-out capab
Page 7 and 8: RM0016 Contents 13.3.1 Beeper contr
Page 9 and 10: RM0016 Contents 17.7.12 Capture/com
Page 11 and 12: RM0016 Contents 19.6.9 Auto-reload
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Page 19 and 20: RM0016 List of figures List of figu
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RM0016 Interrupt controller (ITC) 6
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RM0016 Reset (RST) 8 Reset (RST) Th
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RM0016 Reset (RST) 8.3.2 Watchdog r
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RM0016 Clock control (CLK) 9 Clock
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RM0016 Clock control (CLK) 9.1 Mast
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RM0016 Clock control (CLK) 9.1.3 LS
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RM0016 Clock control (CLK) The SWBS
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RM0016 Clock control (CLK) Figure 2
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RM0016 Clock control (CLK) 9.6 Cloc
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RM0016 Clock control (CLK) 9.9 CLK
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RM0016 Clock control (CLK) 9.9.3 Cl
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RM0016 Clock control (CLK) 9.9.6 Cl
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RM0016 Clock control (CLK) 9.9.8 Pe
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RM0016 Clock control (CLK) 9.9.10 C
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RM0016 Clock control (CLK) 9.9.12 S
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RM0016 Power management 10 Power ma
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RM0016 Power management 10.2.1 Wait
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RM0016 General purpose I/O ports (G
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RM0016 Auto-wakeup (AWU) 12.3 AWU f
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RM0016 Auto-wakeup (AWU) Example 1
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RM0016 Auto-wakeup (AWU) 12.4.3 Tim
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RM0016 Beeper (BEEP) 13.2.2 Beeper
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RM0016 Independent watchdog (IWDG)
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RM0016 Independent watchdog (IWDG)
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RM0016 Window watchdog (WWDG) Figur
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RM0016 Window watchdog (WWDG) Figur
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RM0016 Window watchdog (WWDG) Bits
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RM0016 Timer overview 16.1 Timer fe
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RM0016 Timer overview Table 36. Exp
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RM0016 Revision history 25 Revision
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RM0016 Revision history Table 78. D
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RM0016 Index IWDG_KR . . . . . . .
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RM0016 Please Read Carefully: Infor
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