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STM8S and STM8A microcontroller families

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Central processing unit (CPU)<br />

RM0016<br />

Figure 1.<br />

Programming model<br />

7<br />

0<br />

A ACCUMULATOR<br />

15<br />

XH<br />

8<br />

7<br />

XL<br />

0<br />

X INDEX<br />

15<br />

XH<br />

8<br />

7<br />

XL<br />

0<br />

Y INDEX<br />

15<br />

SH<br />

8<br />

7<br />

S<br />

0<br />

SP STACK POINTER<br />

23<br />

PCE<br />

16 15<br />

PCH<br />

8<br />

7<br />

PCL<br />

0<br />

PC PROGRAM COUNTER<br />

7<br />

0<br />

V 0 I1 H I0 N Z C<br />

CC CODE CONDITION<br />

Stack pointer (SP)<br />

The stack pointer is a 16-bit register. It contains the address of the next free location of the<br />

stack. Depending on the product, the most significant bits can be forced to a preset value.<br />

The stack is used to save the CPU context on subroutine calls or interrupts. The user can<br />

also directly use it through the POP <strong>and</strong> PUSH instructions.<br />

The stack pointer can be initialized by the startup function provided with the C compiler. For<br />

applications written in C language, the initialization is then performed according to the<br />

address specified in the linker file for C users. If you use your own linker file or startup file,<br />

make sure the stack pointer is initialized properly (with the address given in the datasheets).<br />

For applications written in assembler, you can use either the startup function provided by ST<br />

or write your own by initializing the stack pointer with the correct address.<br />

The stack pointer is decremented after data has been pushed onto the stack <strong>and</strong><br />

incremented after data is popped from the stack. It is up to the application to ensure that the<br />

lower limit is not exceeded.<br />

A subroutine call occupies two or three locations. An interrupt occupies nine locations to<br />

store all the internal registers (except SP). For more details refer to Figure 2.<br />

Note:<br />

The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU<br />

is in one of these modes, the latency is reduced.<br />

24/449 Doc ID 14587 Rev 8<br />

www.BDTIC.com/ST

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