STM8S and STM8A microcontroller families

List of figures
RM0016
Figure 47. External trigger input block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 48. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 49. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 50. Control circuit in trigger reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 51. Control circuit in trigger gated mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 52. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 53. Timer chaining system implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 54. Trigger/master mode selection blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 55. Master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 56. Gating timer B with OC1REF of timer A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 57. Gating timer B with the counter enable signal of timer A (CNT_EN) . . . . . . . . . . . . . . . . 160
Figure 58. Triggering timer B with the UEV of timer A (TIMERA-UEV) . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 59. Triggering timer B with counter enable CNT_EN of timer A . . . . . . . . . . . . . . . . . . . . . . 162
Figure 60. Triggering Timer A and B with Timer A TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 61. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 62. 16-bit read sequence for the TIM1_CCRi register in capture mode . . . . . . . . . . . . . . . . . 164
Figure 63. Channel input stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 64. Input stage of TIM 1 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 65. PWM input signal measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 66. PWM input signal measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 67. Channel output stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 68. Detailed output stage of channel with complementary output (channel 1) . . . . . . . . . . . . 169
Figure 69. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 70. Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8) . . . . . . . . . . . . . . . . . 172
Figure 71. Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 72. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 73. Complementary output with deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 74. Deadtime waveforms with a delay greater than the negative pulse . . . . . . . . . . . . . . . . . 176
Figure 75. Deadtime waveforms with a delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 176
Figure 76. Six-step generation, COM example (OSSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 77. Behavior of outputs in response to a break (channel without complementary output) . . . 179
Figure 78. Behavior of outputs in response to a break (TIM1 complementary outputs) . . . . . . . . . . 180
Figure 79. ETR activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 80. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 81. Example of encoder interface mode with IC1 polarity inverted. . . . . . . . . . . . . . . . . . . . . 183
Figure 82. TIM2/TIM3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 83. TIM5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 84. Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 85. Input stage block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 86. Input stage of TIM 2 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 87. Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 88. Output stage of channel 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 89. TIM4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 90. TIM6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 91. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 92. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 93. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 94. TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0).
Case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 95. TXE/RXNE/BSY behavior in slave / full duplex mode
(BDM = 0, RXONLY = 0). Case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 96. TXE/BSY in master transmit-only mode
20/449 Doc ID 14587 Rev 8
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