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Chapter 15 Boz–7 Implementation of the CPU
This leads to a simple statement defining this sequencing signal.
S1 = 0 if and only if the assembly language opcode = 0x0F and branch = 0,
where branch = 1 if and only if the branch condition is met.
The sequencing signal S2 is used to control the entering of the defer code for those
instructions that can use indirect addressing. Recall that the assignment of opcodes to the
assembly language instructions has been structured so that only instructions beginning with
“011” can enter the defer phase. Even these enter the defer phase only when IR 26 = 1.
Thus, we have the following definition of this signal.
S2 = 1 if and only if (IR 31 = 0, IR 30 = 1, IR 29 = 1, and IR 26 = 1)
In a way, this is exactly the definition of the sequencing control signal S 2 as used in the
hardwired control unit. The only difference is that in this design the signal S2 must be used
independently of the signal S1, so we must use the full definition. The figure below
illustrates the circuitry to generate the two sequencing signals S1 and S2.
Given these circuits, we have the final form and labeling of the micro–words in the micro–
memory. Note that there are no “micro–data” words, only microinstructions.
Micro–Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1
4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 8 bit 8 bit
The form of the type 1 instruction is completely defined and can be given as follows.
Micro–Op B1 B2 B3 ALU M1 M2 D = 0 D = 1
0001 0x0 0x0 0x0 0x0 0x0 0x0 0x20 0x20
But what exactly does this dispatch instruction do? The question becomes one of defining
the dispatch table, which is used to determine the address of the microcode that is invoked
explicitly by this dispatch. We now address that issue.
Page 544 CPSC 5155 Last Revised July 9, 2011
Copyright © 2011 by Edward L. Bosworth, Ph.D. All rights reserved.