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Chapter 15 Boz–7 Implementation of the CPU
GET Op-Code = 01000 (Hexadecimal 0x08)
F, T3: WAIT.
E, T0: IR B1, tra1, B3 IOA. // Send out the I/O address
E, T1: WAIT.
E, T2: IOD B2, tra2, B3 R. // Get the results.
E, T3: WAIT.
As noted above, we can ignore any WAIT signal that is not required by considerations of
memory timing. The first of two microoperations is associated with the dispatch address for
the GET instruction and the second one at the first available micromemory word.
IR B1, tra1, B3 IOA.
Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1
0x08 0 4 0 8 1 0 0 0x24 0x24
IOD B2, tra2, B3 R.
Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1
0x24 0 0 7 7 2 0 0 0x20 0x20
PUT Op-Code = 01001 (Hexadecimal 0x09)
F, T3: WAIT.
E, T0: R B2, tra2, B3 IOD // Get the data ready
E, T1: WAIT.
E, T2: IR B1, tra1, B3 IOA. // Sending out the address
E, T3: WAIT. // causes the output of data.
R B2, tra2, B3 IOD
Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1
0x09 0 0 3 7 2 0 0 0x25 0x25
IR B1, tra1, B3 IOA.
Address Micro-Op B1 B2 B3 ALU M1 M2 S2 = 0 S2 = 1
0x25 0 4 0 8 1 0 0 0x20 0x20
RET Op-Code = 01010
(Hexadecimal 0x0A)
F, T3: WAIT
E, T0: SP B1, + 1 B2, add, B3 SP. // Increment the SP
E, T1: SP B1, tra1, B3 MAR, READ. // Get the return address
E, T2: WAIT.
E, T3: MBR B2, tra2, B3 PC. // Put return address into PC
Here we have three non–waiting instructions plus a WAIT that is necessary for the memory
access. As a result, we must allocate four micro–memory words to the execution.
Page 552 CPSC 5155 Last Revised July 9, 2011
Copyright © 2011 by Edward L. Bosworth, Ph.D. All rights reserved.