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Chapter 15 Boz–7 Implementation of the CPU
In the next table, we examine these instructions closely to determine patterns that will be of
use in defining the Major State Register. For all other instructions, the state after Fetch is
Fetch again; the instruction completes execution in one major cycle and the next is fetched.
IR 31 IR 30 IR 29 IR 28 IR 27 IR 26 = 0 IR 26 = 1
GET 0 1 0 0 0 Execute
PUT 0 1 0 0 1 Execute
RET 0 1 0 1 0 Execute
RTI 0 1 0 1 1 Execute
LDR 0 1 1 0 0 Execute Defer
STR 0 1 1 0 1 Execute Defer
JSR 0 1 1 1 0 Execute Defer
BR 0 1 1 1 1 Execute if Branch = 1,
Fetch Otherwise
Defer if Branch = 1,
Fetch Otherwise
We define two generated control signals, S 1 and S 2 , as follows:
1. If the present state is Fetch and S 1 = = 0, the next state will be Fetch.
If the present state is Fetch and S 1 = = 1, the next state is either Defer or Execute.
2. If the present state is Fetch, S 1 = = 1, and S 2 = = 0, the next state will be Execute.
If the present state is Fetch, S 1 = = 1, and S 2 = = 1, the next state will be Defer.
3. Automatic rule: If the present state is Defer, the next state will be Execute.
4. Automatic rule: If the present state is Execute, the next state will be Fetch.
This leads to the following state diagram for the Major State Register.
Figure: State Diagram for the Major State Register
A three–state diagram requires two flip–flops for its implementation. To begin this design,
we assign two–bit binary numbers, denoted Y 1 Y 0 , to each of the major states.
State Y 1 Y 0
F 0 0
D 0 1
E 1 0
Page 526 CPSC 5155 Last Revised July 9, 2011
Copyright © 2011 by Edward L. Bosworth, Ph.D. All rights reserved.