Digital Array Radar Technology for MPAR

Digital Array Radar 

Technology for MPAR 

Dr. William Chappell 

May 11, 2011

Outline 

• Introduction to Digital Array Technology 

– Moore’s Law, Cost, and Performance 

– Standardization and Competition 

– Low-Cost RF Frontend Concept 

• Army DAR Project 

– Digital Beamforming and Adaptability 

– GaN Antenna Panel Integration 

– Digital Backend Enhancements 

• Dual Polarization Measurements 

– Calibration Requirements/ Capabilities 

5/2/2011 

2

Introduction: Digital Array Radar 

Past: Passive Array 

Analog 

Beamformer 

HP 

Duplexer 

LNA 

Tube 

Amp 

Receiver 

and A/D 

Waveform 

Generator 

Processor & 

Controller 

-Phase shifter/attenuator per element 

-Enables fast beam switching 

-Losses on both Tx. & Rx. 

-Fixed, metal beamformer 

-Single points of failure 

5/2/2011 

Images: W. Weedon, Applied Radar, Inc. J. Herd, MIT LL, and S. Kemkemian et. al, Thales, at Phased Array Conf., 2010. www.militaryaerospace.com radar.jpl.nasa.gov 

3



Present: Active Array (Digitized Subarray) 

Analog 


HP 

Duplexer 

LNA 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 






5/2/2011 

Tube 

Amp 


Generator 

Receiver 

and A/D 

Processor & 

Controller 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 

-LNA, HPA, phase shifter, attenuator, 

duplexer, T/R switches per element 

-All RF parts handle less power 

-Lower RF losses 

-More waveform agility 

-”Graceful degradation” 

-Multiple beams possible w/adaptivity 

-Mixing/digitization at subarrays 


4




Analog 


HP 

Duplexer 

LNA 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 






5/2/2011 

Tube 

Amp 


Generator 

Receiver 

and A/D 

Processor & 

Controller 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 










5




Analog 


HP 

Duplexer 

LNA 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 






5/2/2011 

Tube 

Amp 


Generator 

Receiver 

and A/D 

Processor & 

Controller 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 










6




Analog 


HP 

Duplexer 

LNA 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 






5/2/2011 

Tube 

Amp 


Generator 

Receiver 

and A/D 

Processor & 

Controller 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 










7




Analog 


HP 

Duplexer 

LNA 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 






5/2/2011 

Tube 

Amp 


Generator 

Receiver 

and A/D 

Processor & 

Controller 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 










8




Future/Now: Digital Array 






5/2/2011 

HP 

Duplexer 

Tube 

Amp 


Generator 

Analog 


LNA 

Receiver 

and A/D 

Processor & 

Controller 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 









T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

Digital 

Backend 

Proc. & Controller 

-Transceiver, digitizer, and DDS for 

each element 

-Multiple beams and adaptive 

beamforming limited by I/O and 

processing only, not RF hardware 

-Ultimate in waveform agility 

-High dynamic range potential 

-Multiple concurrent functions 


9










5/2/2011 

HP 

Duplexer 

Tube 

Amp 


Generator 

Analog 


LNA 

Receiver 

and A/D 

Processor & 

Controller 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 









Advanced 

Integration 

Difficult to 

functionally 

“separate” 

the sections 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 


Backend 



each element 








10










5/2/2011 

HP 

Duplexer 

Tube 

Amp 


Generator 

Analog 


LNA 

Receiver 

and A/D 

Processor & 

Controller 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 









Advanced 

Integration 

Difficult to 

functionally 

“separate” 

the sections 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 


Backend 



each element 








11

Future Digital Arrays 

• Lower cost 

– panelization of RF + digital 

– modular/open architecture 

– highly-integrated RF with directconversion/low 

IF 

– surface mount technology and 

plastic packaging 

• Advanced functionality 

– digital at each element 

– distributed transceivers 

– self-monitoring of errors 

– multiple functions 

– dual polarization (MPAR) 

– More I/O and processing BW 

5/2/2011 

12






IF 










Moore’s Law 

5/2/2011 

13






IF 










Moore’s Law 

Future challenge: Leverage increasing role of digitization to 

overcome limitations of lower-cost RF and transceiver functions 

5/2/2011 

14

MPAR Needs 

• Programmability 

• Low Cost 

• Standardization 

• Competition 

• Dual Pol 

5/2/2011

Programmability 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

T/R 

Analog 

BF Analog 

BF Analog 

BF 


Generator(s) 

Processor & 

Controller 

Receivers 

and A/D 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

Xcvr. 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 

A/D+DDS 


Backend 


Software programmability – New beamforming and scan strategies. Dynamic 

beamforming capabilities. 

Hardware programmability - monthly/yearly adaptability 

5/2/2011 

16

Cost 

• FPGAs subject to the same 

implications of Moore’s Law as 

other digital circuits 

• Performance and functionality 

improvements derived from 

increased transistor count 

• Current FPGAs achieve needed 

functionality with costs reducing 

over time 

– Technology demonstrator at ~$15 per 

chip and falling 

• Processing technologies provide 

ASIC like performance at a 

reduced cost while allowing for 

FPGA prototyping ease 

– Xilinx EasyPath 

– Altera HardCopy 

Xilinx 1 Million System Gate FPGA Cost 

5/2/2011 

http://www.greentechmedia.com/articles/read/varian-looks-to-enforce-moores-law-in-solar/ 

http://www.xilinx.com/partners/90nm/ 

17

Low Cost RF 

What has changed in the RF world since I started my career: 

1.) RF became a commodity 

2.) Full wave electromagnetic analysis became commonplace 

3.) Silicon dominates the RF landscape 

4.) III-V is starting to be dominated by wideband gap semiconductors 

There is the potential for RF to be very cheap. For the first time, the RF circuit 

is not the domain of the specialist. 

5/2/2011 

18

What Was State of the Art? 

Insert the picture of firsts at ISSCC 

Silicon dominates the RF landscape even up to mmWave

Where is the RF in a commercial system? 

ifixit.com 

The wireless is in the cable 

holding down the battery 

20

ifixit.com 

21

Nearing Commodity Status 

Broadcom 4329 

65 nm CMOS with built in PA’s. Built in digital wireless stack, CPU, ROM 

22

The Challenge for a Low Cost Radar 

• The Challenge is too utilize the capability 

CMOS and SiGE IC’s which are available. 

– Worse performance but better value 

• Can we eliminate the components that make a 

radar unique from commercial wireless 

systems? 

– Phase Shifters, Beam Formers, Circulators/ 

Isolators, Highly Matched T/R Modules 

23

Low-Cost Array Concept 

Traditional Hybrid Radar Module 

~ 


Backend 

Advanced Integration 

A/D 

D/A 

~ 

SiGe 

GaN 

~ 

Traditional 

electronics 

Image from Eurofighter’s radar http://www.airpower.at/news06/0922_captor-e/index.html 

Massively integrated SiGe 

chip transceivers 

High power GaN 

MMIC 

Want low cost integration without sacrificing performance. 

Key technologies are GaN, SiGe, and digital backend integrated 

using traditional electronics manufacturing techniques 

Planar “laptop-like” integration of modules 

and antenna 

5/2/2011 19-May-11

Compound Semiconductor Materials on Silicon (COSMOS) 

Program Objective: Heterogeneous integration all the way to the transistor scale 

• Enable materials selection within circuits – without loss of transistor performance 

• Exploit existing SOA CMOS infrastructure & integration levels – without process modification 

DoD Benefits 

• Achieve higher functional density: dense integration of analog, mixed-signal, & digital electronics 

• Enable circuits with lower dissipated power & far higher I/O throughput 

Flip-chip 

What else may impact cost? 

Today 

COSMOS Vision 

Reflow solder bumps 

Chip size 

~1 mm 

200 μm pitch 

Heterogeneous integration exists only on a very 

coarse scale – and not in the signal path 

Compound 

Semiconductor (CS) 

“Chiplets” 

Si CMOS 

Allow the circuit designer to select the optimal 

transistor technology everywhere in the circuit

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Header Header 

Header Header 

Header Header 

Header Header 

Context for Work: Army DAR Project 

Vision for S-band digital subarray 

Initial subarray demonstrator 

Control 

Quadrant 

Transceiver 

RF 

RS-232 

Spartan 

3AN 

FPGA 

32 Mb 

SRAM 

PC 

JTAG 

Clock 

Dist. 

Spartan 2x DAC 

Spartan 3A 

2x DAC 

FPGA 

Spartan 3A 2x DAC 2x DAC 

FPGA Spartan 3A 

2x DAC 2x DAC 

FPGA 3A 4x ADC 

2x DAC 

2x DAC 

32 Mb 

4x ADC 

FPGA 

2x DAC 

SRAM 32 Mb 

4x ADC 2x DAC 

SRAM 32 Mb 4x ADC 

SRAM 32 Mb 

4x ADC 

SRAM 

2x2 

MIMO 2x2 

Xcvr. MIMO 2x2 


Xcvr. MIMO 

Xcvr. 

2x2 

MIMO 2x2 



Xcvr. MIMO 

Xcvr. 

Sw. GaN 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

5/2/2011 

Five graduate students, two undergraduates, and two faculty 

26

Competition 

• By decoupling from the central beamformer, the 

array subunits could be defined as specs which are 

competed. 

– Competed at any subunit level (2, 4, 16, 64,… element 

panels) 

• Connecting together disparate data sources at the 

digital data level is a standard process 

• Standards dictating the digital data transfer would 

allow for multiple sources 

– Build me the “radiating” laptop with rapid I/O output. 

5/2/2011 

27

Standardization 

Brand Q v1.0 

“Radiating Laptop” 

Brand X v2.0 


Standardized Interface 

Brand D v1.0 


Brand Y v2.0 

Communication 

Network 

Brand Y v1.0 

Communication 

Network 

Brand P v5.0 


Standardized Interface 

Brand Z v3.0 


Brand F v2.0 


Future Implementations 

Fielded Unit 

Phased Out 

• This could be a parallel to a network implementation of laptop’s/ desktop’s 

– Make/ Model / Version of laptop irrelevant as network still functions 

• If you build the “radiating laptop” with standards between units, then there is 

the possibility of the network parallel being a reality. 

5/2/2011 

28

Initial DAR Demonstrator 

16-Element Backend Stats: 

Frequency: 3.1-3.5 GHz 

Inst. BW: 

Antenna Board: 

Antenna Type: 

Backend PCBs: 

A/D resolution: 

Sample rate: 

Control Intfc.: 

Data Intfc: 

Real-time beams: 

Element-level RAM: 

14 MHz direct conversion 

Rogers 4350b & Rohacell 

Stacked patch (apt. fed) 

FR-4 

12 Bits 

24 Msps (I/Q) 

MATLAB (RS-232) 

Gigabit Ethernet 

1 (sum/difference) 

32 Mb 

GaN Panel Stats: 

GaN HPA power: 25 W @ 28V per element 

GaN HPA PAE: >60% 

5/2/2011 

29


Integrated 

Ant./RF Panel 

5/2/2011 

30


Two Channel 

SiGe Transceivers 

Integrated 

Ant./RF Panel 

5/2/2011 

31


Data Conversion/ 

Processing 

Two Channel 


Integrated 

Ant./RF Panel 

5/2/2011 

32


Digital Backend/ 

PC Interface 


Processing 

Two Channel 


Integrated 

Ant./RF Panel 

5/2/2011 

33


Digital Backend/ 

PC Interface 


Processing 

Two Channel 


Integrated 

Ant./RF Panel 

16-Element Backend Stats: 

Frequency: 3.1-3.5 GHz 

Inst. BW: 

Antenna Board: 

Antenna Type: 

Backend PCBs: 

A/D resolution: 

Sample rate: 

Control Intfc.: 

Data Intfc: 

Real-time beams: 

Element-level RAM: 

14 MHz direct conversion 

Rogers 4350b & Rohacell 

Stacked patch (apt. fed) 

FR-4 

12 Bits 

24 Msps (I/Q) 

MATLAB (RS-232) 

Gigabit Ethernet 

1 (sum/difference) 

32 Mb 

GaN Panel Stats: 

GaN HPA power: 25 W @ 28V per element 

GaN HPA PAE: >60% 

5/2/2011 

34

DAR Digital Beamforming 

• Verified digital beamforming on Tx. & Rx. 

• Measured patterns at Lockheed Martin 

5/2/2011 

16 elements demonstrated with transmit and receive. 

Independent digitization of each transmit and receive channel 

35

Army DAR Project Digital Backend 

• Important features 

– Digital at every element 

– Standard PCB processing 

– hierarchical digital 

beamformer 

– distributed directconversion 

transceivers 

5/2/2011 

36

Army DAR Project Digital Backend 

• Important features 

– Digital at every element 

– Standard PCB processing 

– hierarchical digital 


– distributed directconversion 

transceivers 

• Simple example: Bistatic 

tracking 

5/2/2011 

Coupling & clutter 

suppression with 

element-level data 

37

Adaptability 

1101101010010… 

0110010001011… 

• Principle of operation: 

– Use receivers as built-in vector signal analyzers 

– Monitor transmit-receive coupling pair signals 

• Applications: 

– Array self-calibration and calibration monitoring 

– Built-in/automatic I/Q imbalance correction 

• Example: 

– Denote initial (complex) coupling to n th receiver from the m th transmitter as C mn 

– After array has been fielded, make the same recordings (C’ mn ), forming the 

matrix K: 

C ' 

mn 

T 

m 

R 

n 

C 

mn 

K 

mn 

C 

C 

' 

mn 

mn 

T 

m 

R 

n 

T m = error from digital signal to V m on Tx. 

R n = error from V n to digital signal on Rx. 

– Use this matrix to estimate errors in the array (see example ) 

5/2/2011 

38

5/2/2011 

Adaptability 

39 

8 

4 

7 

4 

6 

4 

5 

4 

4 

4 

3 

4 

2 

4 

1 

4 

8 

3 

7 

3 

6 

3 

5 

3 

4 

3 

3 

3 

2 

3 

1 

3 

8 

2 

7 

2 

6 

2 

5 

2 

4 

2 

3 

2 

2 

2 

1 

2 

8 

1 

7 

1 

6 

1 

5 

1 

4 

1 

3 

1 

2 

1 

1 

1 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

T R 

R 

T 

T R 

R 

T 

T R 

T R 

R 

T 

K

5/2/2011 

Adaptability 

40 

Initial 

T = 36C 

8 

4 

7 

4 

6 

4 

5 

4 

4 

4 

3 

4 

2 

4 

1 

4 

8 

3 

7 

3 

6 

3 

5 

3 

4 

3 

3 

3 

2 

3 

1 

3 

8 

2 

7 

2 

6 

2 

5 

2 

4 

2 

3 

2 

2 

2 

1 

2 

8 

1 

7 

1 

6 

1 

5 

1 

4 

1 

3 

1 

2 

1 

1 

1 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

T R 

R 

T 

T R 

R 

T 

T R 

T R 

R 

T 

K

5/2/2011 

Adaptability 

41 

Initial 

T = 36C 

T = 39C 

8 

4 

7 

4 

6 

4 

5 

4 

4 

4 

3 

4 

2 

4 

1 

4 

8 

3 

7 

3 

6 

3 

5 

3 

4 

3 

3 

3 

2 

3 

1 

3 

8 

2 

7 

2 

6 

2 

5 

2 

4 

2 

3 

2 

2 

2 

1 

2 

8 

1 

7 

1 

6 

1 

5 

1 

4 

1 

3 

1 

2 

1 

1 

1 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

T R 

R 

T 

T R 

R 

T 

T R 

T R 

R 

T 

K

5/2/2011 

Adaptability 

42 

Initial 

T = 36C T = 39C T = 45C 

8 

4 

7 

4 

6 

4 

5 

4 

4 

4 

3 

4 

2 

4 

1 

4 

8 

3 

7 

3 

6 

3 

5 

3 

4 

3 

3 

3 

2 

3 

1 

3 

8 

2 

7 

2 

6 

2 

5 

2 

4 

2 

3 

2 

2 

2 

1 

2 

8 

1 

7 

1 

6 

1 

5 

1 

4 

1 

3 

1 

2 

1 

1 

1 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

R 

T 

T R 

R 

T 

T R 

R 

T 

T R 

T R 

R 

T 

K

Adaptability 

K 

T R 

T 

T 

1 

2 

3 

4 

R 

1 

1 

T R 

R 

1 

1 

T R 

T 

T 

1 

2 

3 

4 

R 

2 

T R 

R 

2 

2 

2 

T R 

T 

T 

1 

2 

3 

4 

R 

3 

T R 

R 

3 

3 

3 

T R 

T 

T 

1 

2 

3 

4 

R 

4 

T R 

R 

4 

4 

4 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

5 

T R 

5 

5 

5 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

6 

T R 

6 

6 

6 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

7 

T R 

7 

7 

7 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

8 

8 

T R 

8 

8 

Initial 

Final 

5/2/2011 

T = 36C T = 39C T = 45C T = 50C 

43

Adaptability 

K 

T R 

T 

T 

1 

2 

3 

4 

R 

1 

1 

T R 

R 

1 

1 

T R 

T 

T 

1 

2 

3 

4 

R 

2 

T R 

R 

2 

2 

2 

T R 

T 

T 

1 

2 

3 

4 

R 

3 

T R 

R 

3 

3 

3 

T R 

T 

T 

1 

2 

3 

4 

R 

4 

T R 

R 

4 

4 

4 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

5 

T R 

5 

5 

5 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

6 

T R 

6 

6 

6 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

7 

T R 

7 

7 

7 

T R 

T 

T 

1 

2 

3 

4 

R 

R 

8 

8 

T R 

8 

8 

Initial 

Final 

Radar can self-correct for 

environmental stresses 

Tx: +/- 5 deg. & 0.13 dB 

Rx: +/- 2.0 deg. & 0.2 dB 

5/2/2011 

T = 36C T = 39C T = 45C T = 50C 

44

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Header Header 

Header Header 

Header Header 

Header Header 

Adaptability 

Contro 

l 

RS-232 

Spartan 

3AN 

FPGA 

32 Mb 

SRAM 

PC 

JTAG 

Clock 

Dist. 

Quadrant 


Spartan 3A 

2x DAC 


FPGA 3A 

2x DAC 

2x DAC 

FPGA 

Spartan 3A 

2x DAC 

4x ADC 

2x DAC 

FPGA 3A 

2x DAC 

32 Mb 

4x ADC 2x DAC 

FPGA 

SRAM 32 Mb 

4x ADC 2x DAC 


4x ADC 

SRAM 32 Mb 

SRAM 

Transceiver 

2x2 

MIMO 2x2 



Xcvr. MIMO 

Xcvr. 

2x2 

MIMO 2x2 



Xcvr. MIMO 

Xcvr. 

RF 

Sw. GaN 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

Final 

Matrix Rotation to compensate for 

phase and amplitude 

Beamforming 

(Sum and Difference) 

5/2/2011 

T = 50C

I/Q Imbalance Self-Correction 

• Automated I/Q compensation 

0 

-20 

Rx. Calibration for channel 1, board 1 

Before Cal. 

After Cal. 

0 

-20 



After Cal. 

-40 

-40 

-60 

-60 

-80 

-80 

-100 

-100 

-120 

-10 -5 0 5 10 

freq, MHz 

-120 

-10 -5 0 5 10 

freq, MHz 

0 

0 

• Demonstrates ~10log(N) improvement at beam 



After Cal. 

-20 

After Cal. 

peak 

-20 

-40 

• Enables use of low-cost components 

-60 

5/2/2011 


-40 

-60 


46

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Xcvr. Header 

Header Header 

Header Header 

Header Header 

Header Header 

Adaptability 

Contro 

l 

RS-232 

Spartan 

3AN 

FPGA 

32 Mb 

SRAM 

PC 

JTAG 

Clock 

Dist. 

Quadrant 


Spartan 3A 

2x DAC 


FPGA 3A 

2x DAC 

2x DAC 

FPGA 

Spartan 3A 

2x DAC 

4x ADC 

2x DAC 

FPGA 3A 

2x DAC 

32 Mb 

4x ADC 2x DAC 

FPGA 

SRAM 32 Mb 

4x ADC 2x DAC 


4x ADC 

SRAM 32 Mb 

SRAM 

Transceiver 

2x2 

MIMO 2x2 



Xcvr. MIMO 

Xcvr. 

2x2 

MIMO 2x2 



Xcvr. MIMO 

Xcvr. 

RF 

Sw. GaN 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. GaN Sw. 

Sw. 

Sw. 

Sw. 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

GaN 

5/2/2011 

Matrix Rotation to compensate 

for phase and amplitude 

DC subtraction 

I/Q imbalance 

Beamforming 

(Sum and Difference) 

I' 

n 

Q' 

n 

A 

I 

n 

Q n 

I 

Q 

DC 

DC 

B 

I 

n 

Q n 

1 

1 

I 

Q 

DC 

DC 

0 

-20 

-40 

-60 

-80 

-100 

-120 



After Cal. 

-10 -5 0 5 10 

freq, MHz

Transceiver Block Diagrams 

Current implementation 

Massive integration has 

taken place and promises 

to further consume 

components 

Currently available 

5/2/2011 

http://www.analog.com/static/imported-files/data_sheets/AD9357.pdf 

48

GaN HPA Integration on RF Antenna Panel 

Package is flip-chip bonded 

to multilayer panel 

Heat sink is attached here 

after reflowing package 

Antenna 

ground plane 

Rogers 4350 Package: 

-QFN-like design 

- < 0.2 dB loss 

- R th < 4ºC/W to heat sink 

Measured Packaged Performance (25 

W) 

Heat 

Signal 

High performance maintained in plastic 

package with limited cooling 

5/2/2011 

49

GaN HPA Integration on RF Antenna Panel 

Circulator 

Antenna 

feed 

LNA biasing 

GaN package 

RF switch 

HPA biasing 

SMA 

Package designed for GaN HPA/LNA 

combination MMIC integrated into Rogers 4350b 

PCB panel 

• 51W radiated, 42% efficient overall, 72°C on fancooled 

copper slug. 58.8W output into circulator 

@ 49% efficiency with 40V drain 

• 28W radiated, 40% efficient overall, 52.5°C on 

fancooled copper slug. 32.3W output into 

circulator @ 46% efficiency with 28V drain 

5/2/2011 

50

DAR Polarimetric Testbed 

V 

H 

• Aperture-coupled, stacked-patch antenna used for case study and tests 

– Designed for broadside cross-pol & port-to-port isolation (> -35 dB) 

– Lightweight, panelized, and has wide bandwidth (~3-3.6 GHz) 

– Rogers 4350b feed with Rogers 5880LZ top patch substrate 

– Similar to other proposed elements for MPAR (MIT LL/MaCom) 

5/2/2011 

51

DAR Polarimetric Testbed 

V 

H 

• Aperture-coupled, stacked-patch antenna used for case study and tests 

– Designed for broadside cross-pol & port-to-port isolation (> -35 dB) 

– Lightweight, panelized, and has wide bandwidth (~3-3.6 GHz) 

– Rogers 4350b feed with Rogers 5880LZ top patch substrate 

– Similar to other proposed elements for MPAR (MIT LL/MaCom) 

• Investigations: 

– Bi-static scattering analysis and pattern measurement 

– Large array simulations 

5/2/2011 

52

Scattering Demonstration 

45° 

Tx 

Rx 

Calibration procedure performed for bistatic 

setup shown on the left 

Flat copper sheet used for transmit 

reflection calibration S = I 

C T and C R matrices determined at: 

(AZ,EL) = (35,17) deg. 

(AZ,EL) = (-32,22) deg. 

Both have noticeable polarization issues 

Overall Procedure 

1) Perform calibration & compensation of Tx. & Rx. 

subarrays at angles of interest 

2) Remove compensation and place new target at 

one of those locations 

3) Send out sequential H and V, 14 MHz wide LFM 

chirp waveforms, subtract off (known) mutual 

coupling, and demodulate returns 

4) Apply digital compensation and repeat (2-3) for 

other targets/angles 

5/2/2011 

45° 

53

Scattering Demo Initial Results 

1.18 

0 

0.20 

29 

0.99 

0 

.21 

221 

C T 

0.14 

179 

0.97 

16 

C R 

.16 

15 

1.0 

18 

S 

S s 

1 

0 

0 

1 

5/2/2011 

54


C T 

1.18 

0.14 

0 

179 

0.20 

0.97 

29 

16 

C R 

0.99 

.16 

0 

15 

.21 

1.0 

221 

18 

S 

S s 

1 

0 

0 

1 

S 

2 

cos / 4 cos / 4 sin / 4 1 

S d 

S 

2 

d 

sin / 4 cos / 4 sin / 4 2 

1 

1 

1 

1 

45° 

Greatly improved polarimetric 

characterization of both targets 

5/2/2011 

55


C T 

1.18 

0.14 

0 

179 

0.20 

0.97 

29 

16 

C R 

0.99 

.16 

0 

15 

.21 

1.0 

221 

18 

S 

S s 

1 

0 

0 

1 

S 

2 

cos / 4 cos / 4 sin / 4 1 

S d 

S 

2 

d 

sin / 4 cos / 4 sin / 4 2 

1 

1 

1 

1 



45° 



5/2/2011 

56

Receive Pattern Demo 

• Use mutual coupling compensation to synthesize patterns with low 

sidelobes (-30 dB goal), then do polarimetric compensation: 

Blue: H 

Black: V 

Compare to ideal 

simulated array in free 

space with no mounting 

hardware 

5/2/2011




Blue: H 

Black: V 




hardware 

5/2/2011




Blue: H 

Black: V 




hardware 

5/2/2011 

59

Large Array Simulations 

• Master/slave boundaries allow infinite array to be simulated under scan 

• Use resulting polarimetric fields to predict large-array performance 

Z 

DRb 

5/2/2011 

S 

S 

Tˆ 

HH 

Tˆ 

VH 

Rˆ 

HH 

Rˆ 

VH 

Tˆ 

Tˆ 

HV 

VV 

Rˆ 

Rˆ 

VV 

HV 

2 

2 

d 

d 

ATSR 

STSR 

Z 

~ 

R 

T 

AT 

~ 

R 

HH HH VH HV 

S 

DRb 

~ 

~ 

RVH 

THH 

ATVH 

RVV 

S 

T 

T 

HV 

HV 

AT 

AT 

VV 

VV 

2 

2 

d 

d 

60


• Resulting co-polar and crosspolar 

patterns 

• Performance for an infinite array 

• Performance for a 64x64 array 

using infinite array data: 

• Also shown that finite array simulations 

converge to infinite case 

5/2/2011 ATSR – Encouraging results with no correction 

STSR – Significant Errors 

61


• Resulting co-polar and crosspolar 

patterns 

• Performance for an infinite array 

• Performance for a 64x64 array 

using infinite array data: 

• Also shown that finite array simulations 

converge to infinite case 

5/2/2011 ATSR – Encouraging results with no correction 

STSR – Significant Errors 

62

Large Arrays with Random Errors 

Worst-case results for -45°








5/2/2011 


Potential Re-Configurable HDB Capabilities 

• Digital overlapped subarray capability for fast volume search 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Partial beamforming 

performed at top of 

hierarchy 

Intermediate 


Intermediate 


Aggregation, true time 

delay, etc. is performed at 

mid hierarchy 

5/2/2011 

Final beamformer 

+ RSP 

Final radar signal processor 

with cognitive 

enhancements similar to 

those with analog 

beamformers 

68

Potential Re-Configurable HDB Capabilities 

• Dynamic subarray allocation & 

array partitioning of T/R 

Transmit 

Examples: 

Simultaneous T/R with 

coupling cancellation 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Digitizer + 

low-level 

processor 

Tx 

Rx 

Intermediate 


Intermediate 


Rx across full 

spectrum 

Guard Cells 

Normal Radar 

Final beamformer 

+ RSP 

Arbitrary, dynamic, 

subarray allocation to 

minimize and randomize 

grating lobes over time 

5/2/2011 

69

Current Developments 

• DAR 1.0 

– Being evaluated at U of Oklahoma 

• DAR 1.5 

– DAR 2.0 Transceiver + DAR 1.0 Backend 

– Pulse board for robust testing 

5/2/2011 

70


• DAR 1.0 


• DAR 1.5 



• DAR 2.0 Digital Backend 

– 50 MSPS x 16 I/Q channels 

– 8x real-time beams 

5/2/2011 

71


• DAR 1.0 


• DAR 1.5 






• 9x9 Antenna Panel 

– Dual pol / x-pol optimized 

– Prove-in large array cal 

5/2/2011 

72


• DAR 1.0 


• DAR 1.5 






• 9x9 Antenna Panel 

– Dual pol / x-pol optimized 

– Prove-in large array cal 

• STAR DAR 

– Concurrent multi-functionality 

– Fixed/tunable coupling structures 

– Packaging improvements 

Frequency 

Time 

5/2/2011 

73

DAR Subarray Version 2: Current Plans 

16-Channel Transceiver Board 

16-Channel Digital Board 

• Bandwidth increased to 28 MHz 

• > 50 Msps w/2 GB RAM total 

• Slightly larger FPGAs (Spartan 3A) 

• Element-level equalization 

• 8 Rx beams through high-speed 

interface to parallel proc. network 

• New GaN MMIC package 

Just returned from board house 

Under Development 

74

Initial Conclusions and Plans 

• Possible to achieve Z DR bias < 0.1 dB 

• Must establish good base performance through antenna design 

– Cylindrical array with stacked patch will help limit calibration 

sensitivity 

– Quality array alignment 

• In-situ monitoring & “round-trip” methods will be required 

– Sun, rain, and target-based techniques similar NEXRAD 

– In-situ monitoring to make sure array errors are random 

• Plan: Build larger arrays (9x9) with less mutual coupling effects to further 

probe calibration limits 

We believe that this is a good example for this type of program 

• Flexible 

• Adaptable 

• Low Cost 

5/2/2011 

75

Digital Array Radar Technology for MPAR

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