74F74 - Dual D-type flip-flop

Philips Semiconductors
Dual D-type flip-flop
Product specification
74F74
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX
UNIT
±10%V CC 2.5 V
V OH High-level output voltage V CC = MIN, V IL = MAX, V IH = MIN I OH = MAX
±5%V CC 2.7 3.4 V
±10%V CC 0.30 0.50 V
V OL Low-level output voltage V CC = MIN, V IL = MAX, V IH = MIN I OL = MAX
±5%V CC 0.30 0.50 V
V IK Input clamp voltage V CC = MIN, I I = I IK -0.73 -1.2 V
I I
Input current at maximum input
voltage
V CC = MAX, V I = 7.0V 100 µA
I IH High-level input current V CC = MAX, V I = 2.7V 20 µA
Low-level input Dn, CPn V CC = MAX, V I = 0.5V -0.6 mA
I IL current SDn, RDn V CC = MAX, V I = 0.5V -1.8 mA
I OS Short-circuit output current 3 V CC = MAX -60 -150 mA
I CC Supply current (total) 4 V CC = MAX 11.5 16 mA
NOTES:
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2 All typical values are at V CC = 5V, T amb = 25°C.
3 Not more than one output should be shorted at a time. For testing I OS , the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I OS tests should be performed last.
4 Measure I CC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
V CC = +5.0V
T amb = +25°C
C L = 50pF, R L = 500Ω
LIMITS
V CC = +5.0V ± 10%
T amb = 0°C to +70°C
C L = 50pF, R L = 500Ω
V CC = +5.0V ± 10%
T amb = –40°C to +85°C
C L = 50pF, R L = 500Ω
MIN TYP MAX MIN MAX MIN MAX
f max Maximum clock frequency Waveform 1 100 125 100 90 MHz
t PLH
t PHL
t PLH
t PHL
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RDn to Qn or Qn
Waveform 1
Waveform 2
3.8
4.4
3.2
3.5
5.3
6.2
4.6
7.0
6.8
8.0
6.1
9.0
3.8
4.4
3.2
3.5
7.8
9.2
7.1
10.5
3.8
4.4
3.2
2.5
8.5
9.2
7.5
10.5
UNIT
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
t su (H)
t su (L)
t h (H)
t h (L)
t w (H)
t w (L)
t w (L)
t rec
PARAMETER
Setup time, high or low
Dn to CPn
Hold time, high or low
Dn to CPn
CPn pulse width,
high or low
SDn, RDn pulse width,
low
Recovery time
SDn, RDn to CPn
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 1
V CC = +5.0V
T amb = +25°C
C L = 50pF, R L = 500Ω
LIMITS
V CC = +5.0V ± 10%
T amb = 0°C to +70°C
C L = 50pF, R L = 500Ω
V CC = +5.0V ± 10%
T amb = –40°C to +85°C
C L = 50pF, R L = 500Ω
MIN TYP MAX MIN MAX MIN MAX
2.0
3.0
1.0
1.0
4.0
5.0
2.0
3.0
1.0
1.0
4.0
5.0
Waveform 2 4.0 4.0 4.0 ns
Waveform 3 2.0 2.0 2.0 ns
2.0
3.0
1.0
1.0
4.0
5.0
UNIT
ns
ns
ns
1996 Mar 12 4