F 19 SERVICE MANUAL - Reptips

F 19 SERVICE MANUAL
THIS DOCUMENT IS A PROPERTY
OF INDUSTRIE FORMENTI ITALIA
NO AUTHORIZED MODIFICATIONS
ARE PERMITTED.
CREATED BY E.G.

There are two different types of F19 chassis that are equipped with two
different microcontroller.
These microcontroller are known as ETT having a code SAA5297A and
PAINTER with a code number SAA5553.
From the point of view of the application on the F19 chassis the two type of
microcontroller are substantially having the same performances, the same pinout
, the same firmware but they are not interchangeable as the power supply
are different.
In case of SAA5297A the power supply is 5 V for the SAA5553 is 3.3 V.
Even if the two devices are non interchangeable the two chassis
can be interchanged as the in/out interface are exactly the same.
As the specifications of the two devices are the same and the first version of
the chassis was equipped with the SAA5297A , in this document the
characteristics of it are very much detailed meanwhile there is a very short
description (as an addendum at the end) for the SAA5553.

F19 CHASSIS DESCRIPTION
Summary
The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect
ratio and dimension from 25" up to 34".
As we can see from the block diagram the chassis is equipped with the most recent
Integrated Circuit like the one chip TV processor TDA884x that does include all the low
level signal processing including Video, Audio, synchronisation process, and chroma
decoder . (see more detail at the "TDA884x FAMILY SPECIFICATION" paragraph), and
the Sound Processor TDA9875A that perform all sound function including digital decoding
of NICAM signals. (see more detail at the " TDA9870A & tda9875A MAIN
CHARACTERISTICS" paragraph).
The above mentioned devices are driven by an Integrated Circuit that does include
the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages
RAM. (SAA5297A)
In the F19 chassis there are, besides the stereo one, two possible module that are
performing "FEATURES" like PIP (picture in picture) and / or CTI (colour transients
improvement) and 4 by 3 to 16 by 9 signal processing. One further module is dedicated to
the so called "Zero Power Stand By"
A 26 Key Remote Control is performing the full control for the end- used but can
also be used in " SERVICE MODE" to control and adjust, without open the back cover of
the TV set all the necessary functions.
With the 5 "LOCAL KEY BOARD" button all the end user function can also be
performed
When the TV set is equipped with a PLL tuner the microcontroller recognise it and
the tuning method became a frequency synthesis system if not it work as a voltage tuning
system (provided all necessary components are mounted)
The TV make use of a multilevel MENU (activated both by the Remote Control and
Local Keyboard) using five selectable languages ( Italian, German, English, France, end
Spanish) with which it is possible to control sequentially all video and sound value, to
adjust several parameter like picture format, sound response, sleep timer etc., and to set
others important parameter like standard, select country for automatic tuning and sort etc.
Here below a list of the characteristics of the TV se
E.G.Data creazione 31/10/99 15.38 1 / 7 f19intro

TV SET CHARACTERISTICS (MONO & STEREO )
PICTURE TUBE SIZE :
• 4 : 3 ASPECT RATIO 21” / 25” / 28” / 29” / 34”
• 16 : 9 ASPECT RATIO 28 “ / 32”
• STANDARD
• R.F. (ANTENNA) (FOR FREQ. SYNTH.) CCIR ( B / G/ L / L’ / D / K / I )
• VIDEO (SCART & CINCH)
B / G/ L / L’ / D / K / I / M / N
• COLOUR (MAX. THREE STANDARDS)
PAL / SECAM / NTSC
• SOUND STANDARD:
B / G/ L / L’ / D / K / I
∗ MONO
AM & FM
∗ STEREO
A2 OR NICAM
TUNING SYSTEM SELECTABLE :
FACTORY OPTION
FREQUENCY SYTHETIZER
• TOTAL AVAILABLE CHANNEL NUMBER 200
• CHANNEL IN ONE RF STANDARD UP TO 100
• NUMBER OF PROGRAM 100
• DIRECT PROGRAM & CHANNEL CALL WITH 1, OR 2 OR 3 DIGIT
• PROGRAM & CHANNEL STEP UP AND DOWN YES
• VOLTAGE SYNTHESISER
• CABLE & HYPERBAND CHANNEL
YES
• SWITCHABLE AFC
YES
• AUTOMATIC SEARCH TUNING
YES
• A S T WITH AUTO SORT
YES
AUDIO SECTION
POWER
• MONO
6 W RMS.
• STEREO
2 x 6 W RMS.
EXTERNAL CONNECTION
• HEADPHONE
STEREO SET ONLY
• LOUDSPEAKERS
INTERNAL L.S. SWITCHED
A / V INPUT / OUTPUT
• FRONT PANEL CINCH
A / V INPUT
• I FULL SCART (CVBS, STEREO, RBA)
MULTIMEDIA INPUT OUTPUT
• SCART (CVBS & STEREO IN / OUT)
VCR, HI.FI, SATELLITE, ETC
• SCART A TO SCART B LOOP THROUGH FOR PROGRAMS DUBBING
TXT
PANEUROPEAN CHARACTER SET
• LEVEL 1
8 PAGES
• LEVEL 1,5 (FASTEXT)
7 PAGES
FEATURES
• CTI (COLOUR TRANSIENT IMPROVEMENT) OPTION
• 16:9 TO 4:3 VIDEO COMPRESSION
ONLY FOR 16:9 TV SET
• VERTICAL ZOOM OUT
3 LEVEL
• MENU DRIVEN SYSTEM
• EASY TO USE REMOTE CONTROL
• REMOTE CONTROL WITH “SERVICE” USE NOT ACCESSIBLE TO END USER
• PIP
OPTION
E.G.Data creazione 31/10/99 15.38 2 / 7 f19intro

EEPROM
PCF8582
AUDIO
A U D I O
THIS MODULE IS PRESENT ONLY FOR STEREO SET
2ND SCART
A/V IN/OUT
TDA9875
SCART INTER.
A /V OUT
A/V IN
AUDIO
VIDEO
&
AUDIO
FULL SCART
RGB
AUDIO
TDA1521
TUNER
PLL
MICRO
PIP
SIEMENS
IIC bus
PCA84C841/210
TXT
SAA5281/....
SAA5297A
T.O.P.
PHILIPS
SAW
FILTER
TXT & OSD
R B G
PIP (RGB)
VIDEO PROCESSOR
TDA 8362A
TDA8395TDA844X
S E C A M
D.L. CROMA
TDA4661
POWER SUPPLY
RGB
RGB
(OSD)
VERTICAL
TDA3654
E.W. GEN.
TDA4950
H. DRIVER L.O.T.
BU 508 D
BC 639
TDA 4605 & STH7N80F
CUT-OFF
E H T
TRAFO
V.
H.
F16UPF19.DRW
E.G. 2/02/99
F16 UPDATED F19 BLOCK DIAGRAM
26 V
12 V
140 V
15 V
8 V
VIDEO AMPL.
TDA5112
RGB
EAT
110°

F 19
IIC bus
IIC bus
EEPROM
PCF8584 /
ST2404CB
TUNER
PLL
IIC bus
LOCAL KEY BOARD
E T T
MICROCONTROLLER
& TELETEX 8 PAGES
PIP
OPTION
PIP (RGB)
VIDEO & AUDIO
AUDIO STEREO (NICAM) PROCESSOR
THIS MODULE IS PRESENT ONLY FOR STEREO SET
TXT
& OSD
R B G
I.R. INPUT
F19 BLOCK DIAGRAM
V
I
D
E
O
A
U
D
I
O
I.
F.
SAW
FILTER
I
NTERCARRIER
SAA5297A
TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)
2ND SCART
AUDIO
A/V IN/OUT
A /V OUT
AUDIO
VIDEOSCART
SWITCH LA7955
A/V IN
*IF VIDEO & PLL DEM
*AGC & AFC, MUTE
*AUDIO PLL DEM
*PAL/NTSC (SECAM) DEC.
*B.B CHROMA DELAY LINE
*FULL SCART INTERFACE.
4
TDA 8843(4)
U V
FEATURES MODULE
TDA4566 (CTI)
SAA4981 (16:9 TO 4:3)
OPTION
POWER SUPPLY
H. DRIVER
TDA 4605 & STH7N90F1
AUDIO SCART SWITCH HEF4053
BC 338
RGB
*H & V SYNC PROCESSIG
*FULL IIC BUS CONTROLL FOR:
*AUTO CUT-OFF
*ALL ANALOGUE FUCTIONS
*GEOMETRY CORRECTION
*FEATURES INTERFACE
E-W POWER
BUK474200A
H DRIVE
A/V/ CINCH
(OPTION)
FULL SCART
IIC BUS ONE CHIP VIDEO PROCESSOR
E-W-
E-W DRIVE COIL
DRIVER
TRAFO
150 V
26 V
12 V
8 V
5 V
RGB
CUT-OFF
VERTICAL
TDA8351
L.O.T.
BU 508 D
TDA1521
RGB
VERTICAL
FEEDBACK
2 x 7 W
AUDIO POWER
LINE OUT
(OPTION)
VIDEO AMPL.
TDA5112
V.
H.
H. DEFL.
& E H T
TRAFO
HEADPHONE
E-W LOAD COIL
EAT
CRT
110°
F19BLDIA.DRW
E.G. 17 / 7 / 99

F 19.1
I
IIC bus
IIC bus
EEPROM
PCF8584 /
ST2404CB
TUNER
PLL
IIC bus
LOCAL KEY BOARD
E T T
SAA5297A or
SAA5553M3
MICROCONTROLLER
& 8 PAGES TELETEXT
PIP
OPTION
PIP (RGB)
VIDEO & AUDIO
AUDIO STEREO (NICAM) PROCESSOR
THIS MODULE IS PRESENT ONLY FOR STEREO SET
TXT
& OSD
R B G
I.R. INPUT
F19.1 BLOCK DIAGRAM
V
I
D
E
O
A
U
D
I
O
I.
F.
SAW
FILTER
NTERCARRIER
TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)
2ND SCART
AUDIO
A/V IN/OUT
A /V OUT
AUDIO
VIDEOSCART
SWITCH LA7955
A/V IN
*IF VIDEO & PLL DEM
*AGC & AFC, MUTE
*AUDIO PLL DEM
*PAL/NTSC (SECAM) DEC.
*B.B CHROMA DELAY LINE
*FULL SCART INTERFACE.
4
TDA 8843 (4)
U V
FEATURES MODULE
TDA4566 (CTI)
SAA4981 (16:9 TO 4:3)
OPTION
POWER SUPPLY
H. DRIVER
BC 338
TDA 4605 & STH7N90F1
AUDIO SCART SWITCH HEF4053
150 V
26 V
12 V
8 V
5 V
RGB
*H & V SYNC PROCESSIG
*FULL IIC BUS CONTROLL FOR:
*AUTO CUT-OFF
*ALL ANALOGUE FUCTIONS
*GEOMETRY CORRECTION
*FEATURES INTERFACE
E-W-
E-W POWER
BUK474200A
H DRIVE
A/V/ CINCH
(OPTION)
FULL SCART
IIC BUS ONE CHIP VIDEO PROCESSOR
DRIVER
TRAFO
RGB
CUT-OFF
VERTICAL
TDA8351
E-W DRIVE COIL
L.O.T.
BU 508 D
TDA1521
RGB
VERTICAL
FEEDBACK
2 x 7 W
AUDIO POWER
LINE OUT
(OPTION)
VIDEO AMPL.
TDA5112
V.
H.
H. DEFL.
& E H T
TRAFO
HEADPHONE
E-W LOAD COIL
EAT
CRT
110°
F19BDE&P.DRW
E.G. 22/04/2000

F19 TUNING
&
TELETEXT

SAA529XA FAMILY MAIN CHARACTERISTICS
FEATURES
General
• Single chip microcontroller with integrated teletext decoder
• Single +5 V power supply
• Single crystal oscillator for teletext decoder, display and microcontroller
• Teletext function can be powered-down independent of microcontroller function for
reduced power consumption in standby
• Pin compatibility throughout family.
Microcontroller
• 80C51 microcontroller core
• 16/32/64 kbyte mask programmed ROM
• 256/768/1280 bytes of microcontroller RAM
• Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals
• One 14-bit PWM for Voltage Synthesis Tuner control
• Four 8-bit Analog-to-Digital converters
• 2 high current open-drain outputs for directly driving LEDs etc.
• I 2 C-bus interface
• External ROM and RAM capability on QFP80 package version.
Teletext acquisition
• 1 page and 10 page Teletext version
• Acquisition of 525-line and 625-line World System Teletext, with automatic selection
• Acquisition and decoding of VPS data (PDC system A)
• Page clearing in under 64 s (1 TV line)
• Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7)
• Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT)
end Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)
• Automatic detection of FASTEXT transmission
E.G.Data creazione 01/11/99 17.27 8 / 30 F19MANU.doc

TO CURRENT INTEGRATOR
VOLTAGE SINTESYS ONLY
MENU V - V + P - P +
SAA5297A.DRW
E.G . 17 / 10 / 99
TO X13
FRANCE STD. SWITCH
CTI DETECTOR
16 : 9 DETECTOR
SCART1 / SCART2 SWITCH
SCART 1 / TV
TO SCART 2 SWITCH
FRONT CINCH / SCART1
SWITCH
SCART 1 INPUT DETECTOR
SCART 2 INPUT DETECTOR
HEAD PHONES DETECTOR
STANDARD SWITCH
UHF SUPPLY
(VOLTAGE SINTESYS ONLY)
TV / AV SWITCH
LOCAL KEY BOARD
TV ON / OFF SWITCH
TUNER SUPPLY (V.S. ONLY)
TUNER SUPPLY(V.S. ONLY)
CVBS FROM ANTENNA
CVBS FROM SCART
DATA
SLICER
REF.PIN
SAA5297A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1
AV1 STS.
AV2 STS.
H.P. STS.
SYSTEM
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
P
O
R
T
2
P
O
R
T
3
P
O
R
T
0
PAGE
RAM
MICRO & TXT Block Diagram
ROM RAM TIMER
A/ D
PWM
TXT
INT
B
U
S
T X T DATA
SLICER &
ACQUISITION
P
O
R
T
1
8051
CORE
OSCILLATOR
DISPLAY
TIMING
DISPLAY
SWT 16:9
OSC. SWT.
MSDA
MSCL
SDA 1
INTO
SCL 1
AM/FM
VDDM
RESET
OSCOUT
OSCIN
OSCGND
VDDT
VDDA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
INT. TEST
FRAME
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CHANGE
ASPECT RATIO
TO SWITCH S.C.
FROM 4.43
TO 3.58 MHz
I.R.
5 V from ST-BY
QZ100
12 MHz
MAIN
IIC BUS
IIC BUS
FOR
EEPROM
SOUND STANDARD
SWITCH
FROM
RESESET CIRCUIT
5 V
VERTICAL
FLYBACK
HORIZONTAL
FLYBACK PULSE
TO
TDA884X
RGB REFERENCE
2,5 VVOLTAGE
PIP DETECTOR
NOT CONNECTED
NOT CONNECTED

TO CURRENT INTEGRATOR
VOLTAGE SINTESYS ONLY
MENU V - V + P - P +
LOCAL KEY BOARD
TO X13
FRANCE STD. SWITCH
CTI DETECTOR
16 : 9 DETECTOR
SCART1 / SCART2 SWITCH
SCART 1 / TV
TO SCART 2 SWITCH
FRONT CINCH / SCART1
SWITCH
SCART 1 INPUT DETECTOR
SCART 2 INPUT DETECTOR
HEAD PHONES DETECTOR
STANDARD SWITCH
UHF SUPPLY
(VOLTAGE SINTESYS ONLY)
TV / AV SWITCH
TV ON / OFF SWITCH
TUNER SUPPLY (V.S. ONLY)
TUNER SUPPLY(V.S. ONLY)
CVBS FROM ANTENNA
CVBS FROM SCART
SAA5553.DRW
E.G 22/ 04 / 2000
DATA
SLICER
REF.PIN
SAA5553M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1
AV1 STS.
AV2 STS.
H.P. STS.
SYSTEM
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
P
O
R
T
2
P
O
R
T
3
P
O
R
T
0
PAGE
RAM
MICRO & TXT Block Diagram
ROM RAM TIMER
A/ D
PWM
TXT
INT
B
U
S
T X T DATA
SLICER &
ACQUISITION
8051
CORE
P
O
R
T
1
OSCILLATOR
DISPLAY
TIMING
DISPLAY
SWT 16:9
OSC. SWT.
MSDA
MSCL
SDA 1
INTO
SCL 1
AM/FM
VDDM
RESET
OSCOUT
OSCIN
OSCGND
VDDT
VDDA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
INT. TEST
FRAME
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CHANGE
ASPECT RATIO
TO SWITCH S.C.
FROM 4.43
TO 3.58 MHz
I.R.
5 V from ST-BY
QZ100
12 MHz
MAIN
IIC BUS
IIC BUS
FOR
EEPROM
SOUND STANDARD
SWITCH
FROM
RESESET CIRCUIT
3 V
VERTICAL
FLYBACK
HORIZONTAL
FLYBACK PULSE
TO
TDA884X
RGB REFERENCE
2,5 VVOLTAGE
PIP DETECTOR
NOT CONNECTED
NOT CONNECTED

• Real-time packet 26 engine for processing accented (and other) characters
• Comprehensive Teletext language coverage
• Video signal quality detector.
Teletext Display
• 525-line and 625-line display
• 12 10 character matrix
• Double height, width and size On-Screen Display (OSD)
• Definable border colour
• Enhanced display features including meshing and shadowing
• 260 characters in mask programmed ROM
• Automatic FRAME output control with manual override
• RGB push-pull output to standard decoder ICs
• Stable display via slave synchronisation to horizontal sync and vertical sync.
Additional features of SAA529xA devices
• Wide Screen Signalling (WSS) bit decoding (line 23).
2 GENERAL DESCRIPTION
The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the
Philips’ industry-standard 80C51 microcontroller and are intended for use as the central
control mechanism in a television receiver. They provide control functions for the television
system and include an integrated teletext function.
The teletext hardware has the capability of decoding and displaying both 525-line and 625-
line World System Teletext. The same display hardware is used both for Teletext and On-
Screen Display, which means that the display features give greater flexibility to
differentiate the TV set.
The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes.
Increasing display capability is offered from the SAA5290 to the SAA5497.
TELETEXT DECODER
Data slicer
E.G.Data creazione 01/11/99 17.27 9 / 30 F19MANU.doc

The data slicer extracts the digital teletext data from the incoming analog waveform. This
is performed by sampling the CVBS waveform and processing the samples to extract the
teletext data and clock.
Acquisition timing
The acquisition timing is generated from a logic level positive-going composite sync signal
VCS. This signal is generated by a sync separator circuit which adaptively slices the sync
pulses. The acquisition clocking and timing are locked to the VCS signal using a digital
phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a
signal quality circuit which disables acquisition if poor signal quality is detected.
Teletext acquisition
This family is capable of acquiring 625-line and 525-line World System Teletext see “World
System Teletext and Data Broadcasting System”. Teletext pages are identified by seven
numbers: magazine (page hundreds), page tens, page units, hours tens, hours units,
minutes tens and minutes units. The last four digits, hours and minutes, are known as the
subcode, and were originally intended to be time related, hence their names.
For the ten page device, each packet can only be written into one place in the teletext
RAM so if a page matches more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered matching page request.
At power-up each page request defaults to any page, hold on and error check Mode 0.
Rolling headers and time
When a new page has been requested it is conventional for the decoder to turn the header
row of the display green and to display each page header as it arrives until the correct
page has been found.
Error checking
Before teletext packets are written into the page memory they are error checked. The error
checking carried out depends on the packet number, the byte number, the error check
mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error
occurs in one of the Hamming checked addressing and control bytes in the page header
or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory
is set, to act as an error flag to the software. If uncorrectable errors are detected in any
other Hamming checked data the byte is not written into the memory.
E.G.Data creazione 01/11/99 17.27 10 / 30 F19MANU.doc

Packet 26 processing
One of the uses of packet 26 is to transmit characters which are not in the basic teletext
character set. The family automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the character set, automatically
writes the appropriate character code into the correct location in the teletext memory. This
is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and
so is often referred to as level 1.5.
By convention, the packets 26 for a page are transmitted before the normal packets. To
prevent the default character data overwriting the packet 26 data the device incorporates a
mechanism which prevents packet 26 data from being overwritten.
Fastext detection
When a packet 27, designation code 0 is detected, whether or not it is acquired, the
TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is
required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit.
When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line
transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the
SFR bit.
THE DISPLAY
Introduction
The capabilities of the display are based on the requirements of level 1 teletext, with some
enhancements for use with locally generated on screen displays. The display consists of
25 rows each of 40 characters, with the characters displayed being those from rows 0 to
24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is
displayed at the top of the screen, followed by row 0, but normally memory rows are
displayed in numerical order. The teletext memory stores 8 bit character codes which
correspond to a number of displayable characters and control characters, which are
normally displayed as spaces. The character set of the device is described in more detail
below.
E.G.Data creazione 01/11/99 17.27 11 / 30 F19MANU.doc

(OPTION BYTE 1
BIT 3 SETTED TO 0
EAST EUROPE
CHARACTER SET
NATIONAL OPTION FOR:
POLISH
GERMAN
ESTONIAN
SERBO-CROAT
CZECH
SLOVAKIA
RUMANIAN
WEST EUROPE
CHARACTER SET
NATIONAL OPTION FOR:
ENGLISH
GERMAN
SWEDISH
ITALIAN
FREANCH
SPANISH
TURKISH
(OPTION BYTE 1
BIT 6 SETTED TO 1
WEST
F19 E&WCS.DRW
E.G. 7/11/99
EAST
D
A
PL
CZ
H
Y
R

Character matrix
Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed,
each pixel is 1 12 s wide and 1 TV line, in each field, high.
East/West selection
In common with their predecessors, these devices store teletext pages as a series of 8 bit
character codes which are interpreted as either control codes (to change colour, invoke
flashing etc.) or displayable characters. When the control characters are excluded, this
gives an addressable set of 212 characters at any given time.
National option characters
The meanings of some character codes between 20H and 7FH depend on the C12 to C14
language control bits from the teletext page header.
The interpretation of the C12 to C14 language control bits is dependent on the East/West
bit.
On-Screen Display characters
Character codes 80H to 9FH are not addressed by the teletext decoding hardware. An
editor is available to allow these characters to be redefined by the customer. The
alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when
the ‘graphics’ serial attribute is set. This increases the number of customer definable
characters to 64.
Clock generator
The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration.
The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer
point. A crystal must be used as the feedback element to complete the oscillator circuitry.
It is operated in parallel resonance. XTALIN is the high gain amplifier input and XTALOUT
is the output. To drive the device externally XTALIN is driven from an external source and
XTALOUT is left open-circuit.
E.G.Data creazione 01/11/99 17.27 12 / 30 F19MANU.doc

SOUND I.F.
AM
SOUND
FILTER
12 V
TUNUNG
VOLTAGE
TO PIN 2
TUNER
TO X13
TR500
F204
TR219
R174
12V
TR218
5V
CVBS PIN 6
IC 204
TO PIN 4 IC 201 R128
TO PIN
TO PIN 8 IC 201 R140 R141
10, 11
TR200
IC 200
TR110
TR201
FRON PIN 8 SCART 1
F575
TO PIN 1
IC 204
F576
TR107
TO STEREO
NICAM
MODULE
T
O
T
U
N
E
R
TO PIN 4
IC 10
PIN 5
PIN 3
PIN 4
TR210
TR2
TR 502
TR 501
TR209
TR503
TR111
FROM PIN 8 SCART 2
5V
R146
MENU V - V + P - P +
5V
TO SWITC INT/EX SOUND
TV ON / OFF
CVBS FROM
ANTENNA
CVBS
FROM SCART
TR203
TR211
SAA5297A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1
AV1 STS.
AV2 STS.
H.P. STS.
SYSTEM
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
SWT 16:9
OSC. SWT.
MSDA
MSCL
SDA 1
INTO
SCL 1
AM/FM
VDDM
RESET
OSCOUT
OSCIN
OSCGND
VDDT
VDDA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
COR
INT. TEST
FRAME
MICRO & TXT PERIPHERALS
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CTI &
16:9 MOULE
IIC BUS
IRR100
QZ100
12 MHz
TR 109
IIC BUS
TR206
TR 205
SOUND STDANDARD SWITCH
TR 101
TR 108
R 106
TR 102
R167
D 108
TR 103
D 105
5V
5V ST-BY
FOR VOLTAGE
SISTETIZER ONLY
5 V
TR 208
3.58MHz
EEPROM
IC 101
TR 105
4.43 MHz
TO PIN 10
IC 102
D 102 FLYBACK PULSE
FROM EHT
VERTICAL
BLANKING
FROM PIN 8
IC 5
TO PIN
23, 24, 25
IC 204
F19MTPER.DRW
E.G. 24 /10 /99
TO
PIN 35
IC 204

TR200
TR201
SOUND I.F.
AM
SOUND
FILTER
F204
CVBSPIN 6
IC 204
F575
TO PIN 1
IC 204
F576
TR107
TO STEREO
NICAM
MODULE
TO PIN 4
IC 10
PIN 5
T
O
T
U
N
E
R
PIN 3
PIN 4
12V
TO PIN
10, 11
IC 200
TR210
TR2
TR 502
TR110
TR 501
TR218
12 V
TUNUNG
VOLTAGE
TO PIN 2
TUNER
5V
TR219
TO PIN 4 IC 201
TO X13
R174
R128
TR500
TO PIN 8 IC 201 R140 R141
TR209
TR503
TR111
FRON PIN 8 SCART 1
FROM PIN 8 SCART 2
5V
R146
MENU V - V + P - P +
5V
TO SWITC INT/EX SOUND
TV ON / OFF
CVBS FROM
ANTENNA
CVBS
FROM SCART
TR203
TR211
SAA 5553
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1AM/FM
AV1 STS. VDDM
AV2 STS. RESET
H.P. STS. OSCOUT
SYSTEM OSCIN
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
SWT 16:9
OSC. SWT.
MSDA
MSCL
SDA 1
INTO
SCL 1
OSCGND
VDDT
VSSA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
COR
INT. TEST
FRAME
MICRO & TXT PERIPHERALS
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CTI &
16:9 MOULE
IIC BUS
IRR100
QZ100
12 MHz
TR 109
IIC BUS
SOUND STDANDARD SWITCH
TR 101
TR 108
TR 102
R167
D 108
TR 103
D 105
3,3 V
3,3 V
D 102
5V
TR206
TR 205
TR8
5 V
FOR VOLTAGE
SISTETIZER ONLY
TR7
D5
TR 208
3.58MHz
EEPROM
IC 101
TR 105
R39
2,5V
FLYBACK
FROM EHT
VERTICAL
BLANKING
FROM PIN 8
IC 5
TO PIN
23, 24, 25
IC 204
F19PAPER.DRW
E.G. 22 / 04 /2000
4.43 MHz
TO PIN 10
IC 102
5 V
R40
TO
PIN 35
IC 204
PAINTER

VIDEO
SIGNAL
PROCESSING

F 19
TO PIN 33
IC100
CVBS EF
FOR TXT
TO PIN 24
TR203
IC 100
(CVBS FOR TXT)
TO PIN 9
IC 100
AV1
STATUS
SCART 1
FROM PIN 6
IC100
AV1 / AV2
SWITCH
FROM PIN 7
IC100
AV1 / TV
SWITCH
TO AV2
19
8
15
11
7
16
20
CVBS IN
TV
CVBS
TO PIN 10
IC 100
AV2 STATUS
EF
TR201
EF
TR204
TR211
1
3
EF
TR200
2
EF
4
7
IIC
TR202
EF
VIDEO IN
CINCH
8
12 V
6
5
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SIF
AUDEXT
NC
NC
PLLIF
IFVIDEO OUT
SCL
SDA
DECOUPLING
CHR.IN
EX.CVBS/Y IN
VP1
INT CVBS IN
GND
AUDIO OUT
DECOUPLING
EX. CVBS IN
BLKIN
B OUT
G OUT
R OUT
BCL/VG
R IN
G IN
B IN
RGB INSERT.
Y IN
Y OUT
1/3 0F IC201
LA7955
CVBS IN
CVBS OUT
FOR VOLTAGE SINTHESIS ONLY
TDA884X
I.F.
VIDEO
AGC
AFC
DEM.
IDENT
SOUND
PROCES.
(MONO)
SYNC
PROCES.
V. & H.
TIME
BASE
IIC
TRANSRECEIVER
TR212
EF
20 19
MSD
PAL
(SECAM)
NTSC
C.D. &
RGB
MATRIX
VIDEO
CONTROL
8
EXT RGB
SWITCH
& RGB
DRIVE
SCART 2
DECOUPLING
DEENPHASIS
AGC OUT
DECOPLING
I REF
VERT. RAMP
EHT PROTEC.
IF IN 2
IF IN 1
V. DRIVE A
V. DRIVE B
E - W OUT
GND 2
PH. 1 FILTER
PH. 2 FILTER
H. IN, S.C. OUT
HOR. OUT
DECOUPLING
CVBS 1 OUT
V P 2
DET FILTER
X TAL 2
X TAL 1
S.C. REF OUT
R - Y IN
B - Y IN
R - Y OUT
B - Y OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EF
RGB AMPLIFIER
MODULE
VIDEO SIGNAL PATH
TO CRT
8 V
UV
12 V
IIC
3,57MHz
5 V
1
2
3
4
5
6
7
8
9
TR208
3.58MHz
TR206
4.43MHz
A10
1
2
3
4
5
6
7
8
9
10
11
12
C T I
&
4 : 3
TO
16 : 9
FROM PIN 52
IC 100 4:3 TO 16:9
SWITCH
8 V
TR500
10
11
UHF
VHF H
VHF LTR502
FROM PIN 1
IC 100
TR501
5 V
TR205
FROM EHT
TR503
FROM IC 100
PIN 14, 20, 21
BAND SWITCHING
TR105
FROM
PIN 51
IC 100
F19VIDEP.DRW
E.G. 14 / 11 / 99

Reset signal
The externally applied RESET signal (active HIGH) is used to initialize the microcontroller
core, in addition to the teletext decoder. However, the teletext decoder incorporates a
separate internal reset function which is activated on the rising edge of the analog supply
pin, VDDA . The purpose of this internal reset circuit is to initialize the teletext decoder when
returning from the “text standby mode”.
TDA884X FAMILY SPECIFICATION
FEATURES
The following features are available in all IC’s:
• Multi-standard vision IF circuit with an alignment-freePLL demodulator without external
components
• Alignment-free multi-standard FM sound demodulator(4.5 MHz to 6.5 MHz)
• Audio switch
• Flexible source selection with CVBS switch andY(CVBS)/C input so that a comb filter can
be applied
• Integrated chrominance trap circuit
• Integrated luminance delay line
• Asymmetrical peaking in the luminance channel with a(defeatable) noise coring function
• Black stretching of non-standard CVBS or luminancesignals
• Integrated chroma band-pass filter with switchablecentre frequency
• Dynamic skin tone control circuit
• Blue stretch circuit which offsets colours near whitetowards blue
• RGB control circuit with “Continuous CathodeCalibration” and white point adjustment
• Possibility to insert a “blue back” option when no videosignal is available
• Horizontal synchronization with two control loops andalignment-free horizontal
oscillatoroptimised N2 application.Functionally the IC series is split up is 3 categories,
viz:
E.G.Data creazione 01/11/99 17.27 13 / 30 F19MANU.doc

TUNER
AGC
I.F IN
PLL
FILTER
Deenphasis
EXTERNAL
AUDIO IN
A.F.
54
53
48
49
5
A
F
W
AFA
AFB
2
IF &
TUNER
A G C
VIDEO IF
AMPLIFIER
A F C
Sensitivity
TDA 8844
55
15
DEENPHASIS LINE
Internal
Audio
EXTERNAL
AUDIO
SWITCH
SWT
MONO AUDIO OUTPUT
TUNER T.O.P
gating
calibration
I.F. value
PLL
DEMOD.
& VCO
VIDEO
AMPLIFIER
CVBS OUT
CVBS (int) IN CVBS / Y IN (comb filter)
CVBS OUTPUT CVBS (ext) IN CHROMA IN
VIDEO
IDENT.
AVL
SWITCH &
VOLUME
6
MOD
Pos./Neg.
AVL
Volume
Y DELAY,
C. TRAP,
Y PEAKING
VIDEO
MUTE
13 17 11 10 38
Luma
H. SYNC
SEPARATOR
AUDIO PRE
AMPLIFIER
& MUTE
CVBS & Y/C
SWITCH
To Sync
H. sync
PHI 1
DETECTOR
Chroma
CHROMA
CLOCHE &
BANDPASS
V. SYNC
SEPARATOR
LINE
OSCILL.
VERTICAL
DEVIDER
V. sync
SCL
7 8
IIC
TRANS-
RECEIVER
IIC
SDA
PAL / NTSC
SECAM
DECODER
AUTO
SYSTEM
IDENT.
MANAGER
VERTICAL
SAWTOOTH
GENERATOR
Secam
Decoupling
SAT
MAT
DSA
16
CON
BRI
GAI
Subcarrier
Xtal
34 35
BURST PHASE
DETECTOR
& VCXO
BASE BAND
CHROMA
DELAY LINE
R-Y & B-Y
MATRIX
SAT CONTR.
BLACK STRETCH
SKIN TINT CORR.
RGB SWITCH
RGB CONTROL
AUTO CUT-OFF
& OUTPUT
36
33
28
29
30
27
31
Fsc
Y
B-Y
R-Y
Y
B-Y
32
R-Y
23
R
24
G
25
B
26 F.B.
18
19
20
21
Loop
filter
Phase
Detector
Black
Currente
Input
R
G
B
I
N
P
U
T
O
U
T
P
U
T
AVL
Decoupling
INTER-
CARRIER
IN
(45)
1
BandGap
Decoupling
1 A 10 MHz
B.P.F.
AUDIO
LIMITER
9 12 37 14
8 V Main
Supply
8 V
Supply
Ground
AUDIO
PLL DEM.
56
Sound
Decoupling
43 42 41 40
Phi 1
filter
Phi 2
filter
PHI 2
LINE OUT
S.C. GENER.
Flyback in
Sand
Castle
Out
Line
Pulse
Out
51 52
E - W
GEOMETRY
45
E-W
Vertical
DRIVE
Sawtooth Reference
50
EHT
Overvoltage
VERTICAL
DRIVE
22
47
46
Vertical
Drive
Output
V- Guard &
B.C. limiter
TDA8844BLDIA.DRW
E.G. 17 /10 / 99

• Versions intended to be used in economy TV receiverswith all basic functions (envelope:
S-DIP 56 and QFP 64)
• Versions with additional features like E-W geometrycontrol, H-V zoom function and YUV
interface which are intended for TV receivers with 110° picture tubes(envelope: S-DIP 56)
• Versions which have in addition a second RGB inputwith saturation control and a second
CVBS output (envelope: QFP 64)
• Vertical count-down circuit
• Vertical driver optimised for DC-coupled vertical outputstages
GENERAL DESCRIPTION
The various versions of the TDA 884X/5X series areI 2 C-bus controlled single chip TV
processors which are
intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers.
The N2 version is pin and application compatible with the N1 version, however,a new
feature has been added which makes the N2 more attractive. The IF PLL demodulator has
been replaced byan alignment-free IF PLL demodulator with internal VCO (no tuned circuit
required). The setting of the variousfrequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75
MHz) can be made via the I 2 C-bus.
Because of this difference the N2 version is compatiblewith the N1, however, N1 devices
cannot be used in an optimized N2 application
Functionally the IC series is split up is 3 categories, viz:
• Versions intended to be used in economy TV receivers with all basic functions (envelope:
S-DIP 56 and QFP 64)
• Versions with additional features like E-W geometry control, H-V zoom function and YUV
interface which areintended for TV receivers with 110° picture tubes (envelope: S-DIP 56)
• Versions which have in addition a second RGB input with saturation control and a
second CVBS output (envelope: QFP 64)
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which
is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern
E.G.Data creazione 01/11/99 17.27 14 / 30 F19MANU.doc

IF-IC’s.
The video signal is demodulated by means of an alignment-free PLL carrier regenerator
with an internalVCO. This VCO is calibrated by means of a digital control circuit which
uses the X-tal frequency of the colour decoder as a reference. The frequency setting for
the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 C-
bus. To get a good performance for phase modulated carrier signals the control speed of
the PLL can be increased by means of the FFI bit.
The AFC output is generated by the digital control circuit of the IF-PLL demodulator and
can be read via the I 2 C-bus.
For fast search tuning systems the window of the AFC can be increased with a factor 3.
The setting is realised with the AFW bit. The AFC data is valid only when the horizontal
PLL is in lock (SL = 1)
Depending on the type the AGC-detector operates on top-sync level (single standard
versions) or on top sync and top white- level (multi standard versions). The demodulation
polarity is switched via the I 2 C-bus. The AGC detector time-constant capacitor is
connected externally. This mainly because of the flexibility of the application. The timeconstant
of the AGC system during positive modulation is rather long to avoid visible
variations of the signal amplitude. To improve the speed of the AGC system a circuit has
been included which detects whether the AGC detector is activated every frame period.
When during 3 field periods no action detected the speed of the system is increased. For
signals without peak white information the system switches automatically to a gated black
level AGC. Because a black level clamp pulse is required for this way of operation the
circuit will only switch to black level AGC in the internal mode.
The circuits contain a video identification circuit which is independent of the
synchronisation circuit. Therefore search tuning is possible when the display section of the
receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as
the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a
reliable search system. The ident output is supplied to the tuning system via the I 2 C-bus.
The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the
“internal” CVBS input (see Fig.6).
This has the advantage that the ident circuit can also be made operative when a
scrambled signal is received (descrambler connected between pin 6 (IF video output) and
pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is
not used (e.g. with built-in satellite tuners).
E.G.Data creazione 01/11/99 17.27 15 / 30 F19MANU.doc

The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The
switching between the 2 modes can be realised with the VIM bit.
Video switches
The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When
the Y/C input is not required the Y input can be used as third CVBS input. The switch
configuration is given in Fig.6. The selection of the various sources is made via the I 2 C-
bus.
For the TDA 884X devices the video switch configuration is identical to the switch of the
TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the
TDA884X series) and the I 2 C-bus control is similar to that of the TDA 8374/75. For the
TDA 885X IC’s the video switch circuit has a second output (amplitude of 1 VP-P ) which
can be set independently of the position of the first output. The input signal for the decoder
is also available on the CVBS1-output.
Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for
one of the outputs the luminance and chrominance signals are added so that a CVBS
signal is obtained again.
Sound circuit
The sound bandpass and trap filters have to be connected externally. The filtered
intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL
demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so
that no adjustment is required.
The volume is controlled via the I 2 C-bus. The deemphasis capacitor has to be connected
externally. The non-controlled audio signal can be obtained from this pin (via a buffer
stage).
The FM demodulator can be muted via the I 2 C-bus. This function can be used to switchoff
the sound during a channel change so that high output peaks are prevented.
The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which
automatically stabilises the audio output signal to a certain level which can be set by the
viewer by means of the volume control. This function prevents big audio output fluctuations
due to variations of the modulation depth of the transmitter. The AVL function can be
activated via the I 2 C-bus.
Synchronisation circuit
E.G.Data creazione 01/11/99 17.27 16 / 30 F19MANU.doc

The sync separator is preceded by a controlled amplifier which adjusts the sync pulse
amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at
50% of the amplitude. The separated sync pulses are fed to the first phase detector and to
the coincidence detector. This coincidence detector is used to detect whether the line
oscillator is synchronised and can also be used for transmitter identification. This circuit
can be made less sensitive by means of the STM bit. This mode can be used during
search tuning to avoid that the tuning system will stop at very weak input signals. The first
PLL has a very high statical steepness so that the phase of the picture is independent of
the line frequency.
The horizontal output signal is generated by means of an oscillator which is running at
twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the
incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or
slow). If required the IC can select the time-constant depending on the noise content of the
incoming video signal.
The free-running frequency of the oscillator is determined by a digital control circuit which
is locked to the reference signal of the colour decoder. When the IC is switched-on the
horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress
bytes have been sent. When the frequency of the oscillator is correct the
horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off
behaviour of the horizontal output stage the horizontal output frequency is doubled during
switch-on and switch-off (slow start/stop). During that time the duty cycle of the output
pulse has such a value that maximum safety is obtained for the output stage.
To protect the horizontal output transistor the horizontal drive is immediately switched off
when a power-on-reset is detected. The drive signal is switched-on again when the normal
switch-on procedure is followed, i.e. all sub-address bytes must be sent and after
calibration the horizontal drive signal will be released again via the slow start procedure.
When the coincidence detector indicates an out-of-lock situation the calibration procedure
is repeated.
The circuit has a second control loop to generate the drive pulses for the horizontal driver
stage. The horizontal output is gated with the flyback pulse so that the horizontal output
transistor cannot be switched-on during the flyback time.
Via the I 2 C-bus adjustments can be made of the horizontal and vertical geometry. The
vertical sawtooth generator drives the vertical output drive circuit which has a differential
output current. For the E-W drive a single ended current output is available. A special
E.G.Data creazione 01/11/99 17.27 17 / 30 F19MANU.doc

feature is the zoom function for both the horizontal and vertical deflection and the vertical
scroll function which are available in some versions. When the horizontal scan is reduced
to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched
on to obtain well defined edges on the screen.
Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When
an overvoltage condition is detected the horizontal output drive signal will be switched-off
via the slow stop procedure but it is also possible that the drive is not switched-off and that
just a protection indication is given in the I 2 C-bus output byte.
The choice is made via the input bit PRD. The IC’s have a second protection input on the
ϕ2 filter capacitor pin. When this input is activated the drive signal is switched-off
immediately and switched-on again via the slow start procedure. For this reason this
protection input can be used as “flash protection”.
The drive pulses for the vertical sawtooth generator are obtained from a vertical
countdown circuit. This countdown circuit has various windows depending on the incoming
signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be
forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals
the maximum vertical frequency is increased to 72 Hz so that the circuit can also
synchronise on signals with a higher vertical frequency like VGA. To obtain short switching
times of the countdown circuit during a channel change the divider can be forced in the
search window by means of the NCIN bit. The vertical deflection can be set in the deinterlace
mode via the I 2 C bus. To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam
current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is
set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is
connected thisguard circuit will also blank the output signals. This can be overruled by
means of the EVG bit.
Chroma and luminance processing
The circuits contain a chroma bandpass and trap circuit. The filters are realised by means
of gyrator circuits and
they are automatically calibrated by comparing the tuning frequency with the X-tal
frequency of the decoder. The luminance delay line and the delay for the peaking circuit
are also realised by means of gyrator circuits. The centre frequency of the chroma
bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for
E.G.Data creazione 01/11/99 17.27 18 / 30 F19MANU.doc

“front-end” signals and external CVBS signals. During SECAM reception the centre
frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier
frequencies. All IC’s have a black stretcher circuit which corrects the black level for
incoming video signals which have a deviation between the black level and the blanking
level (back porch). The timeconstant for the black stretcher is realised internally.
The resolution of the peaking control DAC has been increased to 6 bits. All IC’s have a
defeatable coringfunction in the peaking circuit. Some of these IC’s have a YUV interface
(see table on page 2) so that picture improvement IC’s like the TDA 9170 (Contrast
improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be
applied. When the CTI IC’s are applied it is possible to increase the gain of the luminance
channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals
are not affected.
Colour decoder
Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or
PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal
oscillator, a killer circuit and two colour difference demodulators. The 90° phase shift for
the reference signal is made internally.
The IC’s contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I 2
C-bus and which prevents that oversaturation occurs when signals with a high chroma-toburst
ratio are received. The ACL circuit is designed such that it only reduces the chroma
signal and not the burst signal. This has the advantage that the colour sensitivity is not
affected by this function. The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is
obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running
frequency and the bandgap reference to obtain the correct absolute value of the output
signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC
is in search or SECAM mode.
The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune
an external comb filter (e.g. the SAA 4961).
The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM IC’s and in
the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance
(chroma comb filter). The demodulated colour difference signals are internally supplied to
the delay line. The colour difference matrix switches automatically between PAL/SECAM
and NTSC, however, it is also possible to fix the matrix in the PAL standard.
E.G.Data creazione 01/11/99 17.27 19 / 30 F19MANU.doc

The “blue stretch” circuit is intended to shift colour near “white” with sufficient contrast
values towards more blue to obtain a brighter impression of the picture.
Which colour standard the IC’s can decode depends on the external X-tals. The X-tal to be
connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and
pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency
is used to tune the line oscillator the value of the X-tal frequency must be given to the IC
via the I 2 C-bus. It is also possible to use the IC in the so called “Tri-norma” mode for
South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin
35. The switching between the 2 latter X-tals must be done externally. This has the
consequence that the search loop of the decoder must be controlled by the µ-computer.
To prevent calibration problems of the horizontal oscillator the external switching between
the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable
calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA
and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so
that the software can check the I 2 C-bus transmission.
Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the
colour killer is activated although the colour PLL is still in lock. When this killing action is
not wanted it is possible to overrule the colour killer by forcing the colour decoder to the
required standard and to activate the FCO-bit (Forced Colour On) in the control-5
subaddress.
The IC’s contain a so-called “Dynamic skin tone (flesh) control” feature. This function is
realised in the YUV domain by detecting the colours near to the skin tone. The correction
angle can be controlled via the I 2 C-bus.
RGB output circuit and black-current stabilisation
The colour-difference signals are matrixed with the luminance signal to obtain the RGBsignals.
The TDA 884X devices have one (linear) RGB input. This RGB signal can be
controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the
insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the
insertion pin has a high level or not.
The TDA 885X IC’s have an additional RGB input. This RGB signal can be controlled on
contrast, saturation and brightness. The insertion blanking of this input can be switched-off
by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high
level or not.
E.G.Data creazione 01/11/99 17.27 20 / 30 F19MANU.doc

The output signal has an amplitude of about 2 volts black-to-white at nominal input signals
and nominal settings of the controls. To increase the flexibility of the IC it is possible to
insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is
controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64
envelope). This blanking action at the RGB outputs has some delay which must be
compensated externally.
To obtain an accurate biasing of the picture tube a “Continuous Cathode Calibration”
circuit has been developed. This function is realised by means of a 2-point black level
stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting
cathode currents with 2 different reference currents the influence of the picture tube
parameters like the spread in cut-off voltage can be eliminated.
This 2-point stabilisation is based on the principle that the ratio between the cathode
currents is coupled to the ratio between the drive voltages according to:
[ I ki / I k2 ] = [ V dr1 / V dr2 ]
The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the
ratio between the reference currents (which are internally fixed) by changing the (black)
level and the amplitude of the RGB output signals via 2 converging loops. The system
operates in such a way that the black level of the drive signal is controlled to the cut-off
point of the gun so that a very good grey scale tracking is obtained. The accuracy of the
adjustment of the black level is just dependent on the ratio of internal currents and these
can be made very accurately in integrated circuits. An additional advantage of the 2-point
measurement is that the control system makes the absolute value of Ik1 and Ik2 identical
to the internal reference currents. Because this adjustment is obtained by means of an
adaption of the gain of the RGB control stage this control stabilises the gain of the
complete channel (RGB output stage and cathode characteristic).
As a result variations in the gain figures during life will be compensated by this 2-point
loop.
An important property of the 2-point stabilisation is that the off-set as well as the gain of
the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the
cathode is fixed by the relation between the test pulses, the reference current and the
relative gain setting of the 3 channels. This has the consequence that the drive level of the
CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different
picture tubes may require different drive levels the typical “cathode drive level” amplitude
can be adjusted by means of an I 2 C-bus setting. Dependent on the chosen cathode drive
E.G.Data creazione 01/11/99 17.27 21 / 30 F19MANU.doc

level the typical gain of the RGB output stages can be fixed taking into account the drive
capability of the RGB outputs (pins 19 to 21). More details about the design will be given in
the application report.
The measurement of the “high” and the “low” current of the 2- point stabilisation circuit is
carried out in 2 consecutive fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 µA When the TV receiver is switched-on the
RGB output signals are blanked and the black current loop will try to set the right picture
tube bias levels. Via the AST bit a choice can be made between automatic start-up or a
start-up via the µ-processor. In the automatic mode the RGB drive signals are switched-on
as soon as the black current loop
has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised.
The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mod some
delay can be introduced between the setting of the BCF bit and the switching of the AST
bit so that switch-on effects can be suppressed. It is also possible to start-up the devices
with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is
activated with the BCO bit.
The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the
flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking
can be increased to the same value as that of the 50 Hz blanking. This can be set by
means of the LBM bit.
For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When
this bit is activated the black current loop is switched-off, a fixed black level is inserted at
the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed
on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the
different requirements for the optimum cut-off voltage of the picture tube the RGB output
level is adjustable when the VSD bit is activated. The control range is 2.5 ± 0.7 V and can
be controlled via the brightness control DAC. It is possible to insert a so called “blue back”
back-ground level when no video is available. This feature can be activated via the BB bit
in the control2 subaddress.
E.G.Data creazione 01/11/99 17.27 22 / 30 F19MANU.doc

F 19
TO PIN 33
IC100
CVBS EF
FOR TXT
TO PIN 24
TR203
IC 100
(CVBS FOR TXT)
TO PIN 9
IC 100
AV1
STATUS
SCART 1
FROM PIN 6
IC100
AV1 / AV2
SWITCH
FROM PIN 7
IC100
AV1 / TV
SWITCH
TO AV2
19
8
15
11
7
16
20
CVBS IN
TV
CVBS
TO PIN 10
IC 100
AV2 STATUS
EF
TR201
EF
TR204
TR211
1
3
EF
TR200
2
EF
4
7
IIC
TR202
EF
VIDEO IN
CINCH
8
12 V
6
5
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SIF
AUDEXT
NC
NC
PLLIF
IFVIDEO OUT
SCL
SDA
DECOUPLING
CHR.IN
EX.CVBS/Y IN
VP1
INT CVBS IN
GND
AUDIO OUT
DECOUPLING
EX. CVBS IN
BLKIN
B OUT
G OUT
R OUT
BCL/VG
R IN
G IN
B IN
RGB INSERT.
Y IN
Y OUT
1/3 0F IC201
LA7955
CVBS IN
CVBS OUT
FOR VOLTAGE SINTHESIS ONLY
TDA884X
I.F.
VIDEO
AGC
AFC
DEM.
IDENT
SOUND
PROCES.
(MONO)
SYNC
PROCES.
V. & H.
TIME
BASE
IIC
TRANSRECEIVER
TR212
EF
20 19
MSD
PAL
(SECAM)
NTSC
C.D. &
RGB
MATRIX
VIDEO
CONTROL
8
EXT RGB
SWITCH
& RGB
DRIVE
SCART 2
DECOUPLING
DEENPHASIS
AGC OUT
DECOPLING
I REF
VERT. RAMP
EHT PROTEC.
IF IN 2
IF IN 1
V. DRIVE A
V. DRIVE B
E - W OUT
GND 2
PH. 1 FILTER
PH. 2 FILTER
H. IN, S.C. OUT
HOR. OUT
DECOUPLING
CVBS 1 OUT
V P 2
DET FILTER
X TAL 2
X TAL 1
S.C. REF OUT
R - Y IN
B - Y IN
R - Y OUT
B - Y OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EF
RGB AMPLIFIER
MODULE
VIDEO SIGNAL PATH
TO CRT
8 V
UV
12 V
IIC
3,57MHz
5 V
1
2
3
4
5
6
7
8
9
TR208
3.58MHz
TR206
4.43MHz
A10
1
2
3
4
5
6
7
8
9
10
11
12
C T I
&
4 : 3
TO
16 : 9
FROM PIN 52
IC 100 4:3 TO 16:9
SWITCH
8 V
TR500
10
11
UHF
VHF H
VHF LTR502
FROM PIN 1
IC 100
TR501
5 V
TR205
FROM EHT
TR503
FROM IC 100
PIN 14, 20, 21
BAND SWITCHING
TR105
FROM
PIN 51
IC 100
F19VIDEP.DRW
E.G. 14 / 11 / 99

IC204 TDA884X
26 23/24/25 19/20/21 18
F19 RGB AMPLIFIER
12 V
200 V
TO G1 TRC
RGB
IN
RGB
OUT
2
3
1
FAST
BLK.
IN
R17,R18,R19
RGB IN FROM SCART
R215
R216
R217
R600
2
6/11/14
5
D800, D801, D802
9/12/15
E.F.
4 / 5 / 6
R613
R614
R615
1/3/4
7/10/13
TO
RGB
KATODE
R604
R605
R606
STV 5112
F19 RGBCO.DRW
E.G. 14 / 11 /99
3 X

F 19 FEATURE MODULE
Colour Transient Improvment
&
4 : 3 to 16 : 9 Signal Processing

SAA4981
Monolithic integrated 16 : 9
Compressor
FEATURES
• Fixed horizontal compression by a factor of 4 ¤3 for most video standards
• Three fixed screen positions (left, centre and right)
• 5 MHz bandwidth
• Bypass function
• Inputs for luminance and chrominance of side panels
• Standard video inputs and outputs (Y, (Β-Y) and (Ρ-Y))
• Horizontal and vertical sync signals are not processed
• Pre filters and post filters on chip.
GENERAL DESCRIPTION
The integrated 16 : 9 compressor is an IC which compresses the active part of a video line
by a factor of 4 ¤3 from, for example, 52 ms to 39ms. This is necessary to display 4:3
video software on a 16 : 9 tube in the correctproportion. The capacitively coupled video
inputs are Y, (Β-Y) and (Ρ-Y).
The synchronisation input HREF is a line frequencyreference signal. The bandwidth of the
IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched
Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y,
(Β Y) and (Ρ-Y) and provides the following two possibilities:
1. Bypass function (the input signal is not compressed)
2. Compressed video by a factor of 4 ¤3 with three different fixed screen positions (left,
centre and right). The luminance and chrominance of the side panels are determined by
the external signals YSIDE, BYSIDE and RYSIDE.
The horizontal compression is a time discrete and amplitude continuous signal processing.
This provides pre and post filters which are realized on-chip.
FUNCTIONAL DESCRIPTION
SAA4981 16:9 TO 4:3 PROCESSOR Pagina 1 di 3 e.g.SAA4981R.doc

V CCA
V EEA
V CCD
V EED SUB
20 19 8 7 4
YIN
23
CLAMP
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
SC LINE MEMORY
MUX
SC LINE
MEMORIES
6.7 MHz
LOW-PASS FILTER
MUX Y
18
YOUT
SAA4981
C1 C2 C3
B-Y)IN
22
CLAMP
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
SC LINE MEMORY
MUX
SC LINE
MEMORIES
6.7 MHz
LOW-PASS FILTER
MUX BY
17
(B-Y)OUT
C1 C2 C3
R-Y)IN
21
CLAMP
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
SC LINE MEMORY
MUX
SC LINE
MEMORIES
6.7 MHz
LOW-PASS FILTER
MUX RY
16
(R-Y)OUT
HREF
6
HORIZONTAL
SEPARATION
C1
3
C1 C2 C3
54 MHz
PLL
CONTROLLER
C2
C3
CLAMP REFERENCE
3
12
9
10
11 1 2 3 24 5 15 14 13
MHA277
TEST CTRL2
CTRL1 CTRL3
pagewidth
C LMY
CLMBY
C LMRY
BGREFCLAOUT
BYSIDE
YSIDE RYSIDE

Applicable video standards
The integrated 16 : 9 compressor can be used for the following video standards; B, C, D,
G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reducedvideo bandwidth
above 5 MHz.
Clamping circuit
The clamping circuits clamp the video input signals Y, (Β-Y) and (Ρ-Y) to the DC level of
the clamp reference signal fed from the clamp reference circuit. This is necessary to
ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass
filters and the SC line memories.
Internal pre filters
Before the signals are sampled in the time discrete and amplitude continuous area, lowpass
filtering is necessary to avoid any aliasing. Even if the inputs have already been lowpass
filtered further filtering is advantageous for the electromagnetic compatibility (EMC).
The same transfer function is used for all three low-pass filters because of the same
bandwidth for the luminance and chrominance signals (up to 5 MHz)
SC line memories
After the low-pass filters the input signals are fed to the SC line memories. The signals are
sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a
clock frequency of 18 MHz in the compression mode. The result of the different clock
frequencies is a horizontal compression by a factor of 4 ¤3 . The clocks and the horizontal
starting pulses for the SC line memories are fed from the controller.
Two line memories are required for each signal path because in the compression mode, in
one video line the signals are sampled to the SC line memories with 13.5 MHz and one
video line later the signals are read with 18 MHz. In the bypass mode, via the SC line
memories, in one video line the signals are sampled with 13.5 MHz and one video line
later the signals are read with 13.5 MHz.
The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a
multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to
the internal post filters.
Output multiplexer MUX Y, MUX (Β-Y) and MUX (Ρ-Y)
SAA4981 16:9 TO 4:3 PROCESSOR Pagina 2 di 3 e.g.SAA4981R.doc

The output multiplexers are controlled via C1 and C2 fed from the controller. The
multiplexers are used to connect one of the four input signals to the output and, also,
enable fast switching.
The input signals of the multiplexers for one component
• The output signal of the post filter
• The uncompressed signal after the input clamping
• The clamping reference signal
• The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE.
The horizontal separation circuit
The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which
is generated in the positive edge of the burst key of a sandcastle signal.
54 MHz horizontal PLL
The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for
the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHzclock and the
18 MHz clock are line locked.
Clamp reference
Reference voltages are generated In the clamp reference block. These DC signals are
used in the clamping circuits as input signals for the output multiplexers and as reference
voltages for the SC line memories. Four external capacitors at the pins CLMY , CLMBY ,
CLMRY and BGREF respectively are necessary to provide smoothing for the reference
voltages. A black level reference signal is available at CLAOUT.
Controller
The controller generates the clocks and the horizontal start signals for the SC line
memories and, also, the control signals for the output multiplexers. The timing for the start
reading signal for three different screen positions (left, centre and right) and the control
signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass
via the SC line memories and a bypass not via the SC line memories is available. When
the signals do not pass the line memories, the frequencyresponse is not affected by the sifunction.
SAA4981 16:9 TO 4:3 PROCESSOR Pagina 3 di 3 e.g.SAA4981R.doc

HREF
1.5 µs
1.5 µs
64 µs
sampled video
(2)
(1)
(2)
49 µs (used for compression)
6.3 µs
52 µs
side
panel
36.75 µs
compressed video
(centre position)
side
panel
side
panel
compressed video
(right position)
compressed video
(left position)
side
panel
bypassed video
(bypass via the Line Memories)
bypassed video
(2)
(1)
(2)
(full bypass not through the Line Memories)
MHA278

TDA4566
Colour transient improvement circuit
GENERAL DESCRIPTION
The TDA4566 is a monolithic integrated circuit for colour-transient improvement (CTI) and
luminance delay line in gyrator technique in colour television receivers.
Features
• Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient
detecting-, storage- and switching stages resulting in high transients of colour difference
output signals
• A luminance signal path (Y) which substitutes the conventional Y-delay coil with an
integrated Y-delay line
• Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine
adjustment of 37 ns
• Two Y output signals; one of 180 ns less delay
TDA4566 CTI Pagina 1 di 1
e.g.TDA4566R.doc

F19 CTI & 16:9 TO 4 : 3 COMPRESSOR
6
9
8
1
2
12 V
Y
R-Y
B-Y
IC2 TDA4566
15 13
THESHOLD SWT.
14 10
17
1
CLAMP
dV/dt
dV/dt
GYRATOR
DELAY CELLS
7 x 90 ns
INTEGRATOR
& PULSE
FORMER
t = 180 ns
SWT. &
STORE
SWT. &
STORE
2 3 4 5 6 9 18
12
11
8
7
Y
R-Y
B-Y
IC 1
23
22
21
6
CLAMP
CLAMP
CLAMP
HOR.
SEPAR.
SAA4981
LPF
LPF
LPF
54 MHz
PLL
LINE MEMORY
LINE MEMORY
LINE MEMORY
LINE MEMORY
LINE MEMORY
LINE MEMORY
CONTROLLER
20 8
MUX
MUX
MUX
LPF
LPF
LPF
MUX
MUX
MUX
CLAMP
REFERENCE
18
17
16
13
14
5 V
Y OUT
R-Y
OUT
B-Y
OUT
10
7
4
3
7 20 4 12 11 10 9 19 1 2 3 24 5
15
5
11
8 V
R4
S.C INPUT
C10
16
14
13
DUAL MONOSTABLE
MULTIVIBRATOR
M.M.
15
JS 7
JS 6
JS 5
8 16 1
M.M.
3 5
10
2
H REF
5 V
T2
EF
C9
R2
IC 4 HEF 4538
8 V
D1
TR1
12 V
16:9 TO 4:3 SWITCH SIGNAL
note:
If CTI ( IC 2 TDA4566 IS NOT
PRESENT THAN JS 5, JS 6 & JS7
MUST BE INSERTED
F19FEAT.DRW
E.G. 12/12/99
12

SCANNING
SECTION

TDA8351
DC-coupled vertical deflection
Circuit
FEATURES
Few external components
Highly efficient fully DC-coupled vertical output bridge circuit
Vertical flyback switch
Guard circuit
Protection against:
• short-circuit of the output pins (7 and 4)
• short-circuit of the output pins to VP
• Temperature (thermal) protection
• High EMC immunity because of common mode inputs
• A guard signal in zoom mode.
•
GENERAL DESCRIPTION
The TDA8351 is a power circuit for use in 9and 11 colour deflection systems for
field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection
output circuit, operating as a highly efficient class G system.
FUNCTIONAL DESCRIPTION
The vertical driver circuit is a bridge configuration. The deflection coil is connected
between the output amplifiers, which are driven in phase opposition. An external resistor
(RM ) connected in series with the deflection coil provides internal feedback information.
The differential input circuit is voltage driven. The input circuit has been adapted to enable
it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and
TDA8376 which deliver symmetrical current signals. An external resistor (RCON )
connected between the differential input determines the output current through the
deflection coil.
TDA8351 VERTICAL OUTPUT Pagina 1 di 2 e.g.TDA8351R

The relationship between the differential input current and the output current is defined by:
Idiff RCON =Icoil RM .
The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM . The maximum
input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V
(typ). This is recommended because of the spread of input current and the spread in the
value of RCON .
The flyback voltage is determined by an additional supply voltage VFB . The principle of
operating with two supply voltages (class G) makes it possible to fix the supply voltage VP
optimum for the scan voltage and the second supply voltage VFB optimum for the flyback
voltage. Using this method, very high efficiency is achieved.
The supply voltage VFB is almost totally available as flyback voltage across the coil, this
being possible due to the absence of a decoupling capacitor (not necessary, due to the
bridge configuration). The output circuit is fully protected against the following:
thermal protection
• short-circuit protection of the output pins (pins 4 and 7)
• short-circuit of the output pins to VP .
A guard circuit VO(guard) is provided. The guard circuit is activated at the following
conditions:
• during flyback
• during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7)
to VP or ground
• during open loop
• when the thermal protection is activated. This signal can be used for blanking the
picture tubescreen.
TDA8351 VERTICAL OUTPUT Pagina 2 di 2 e.g.TDA8351R

th
V P
V FB
V O(guard)
7
3 8
6
V P
CURRENT
SOURCE
TDA8351
V P
V O(A)
V O(A)
I drive(pos)
I drive(neg)
1
2
I S
I T
I
T
V P
9
V I(fb)
V
I
S
V O(B)
4
V O(B)
5
GND
MBC988- 1

PINNING
SYMBOL PIN DESCRIPTION
I drive(pos) 1 input power-stage (positive);
includes I I(sb) signal bias
I drive(neg) 2 input power-stage (negative);
includes I I(sb) signal bias
V P 3 operating supply voltage
V O(B) 4 output voltage B
GND 5 ground
V FB 6 input flyback supply voltage
V O(A) 7 output voltage A
V O(guard) 8 guard output voltage
V I(fb) 9 input feedback voltage
handbook, 2 columns
I drive(pos) 1
I drive(neg)
V P
VO(B)
GND
V FB
V O(A)
VO(guard)
V I(fb)
2
3
4
5
6
7
8
9
TDA8351
MBC989

IC 204
TDA8844
28 V
146 V
HEATER
VOLTAGE
11
12
1
T 3
EHT
FOCUS
20 mS
IC 5 TDA8351
1
2
3
4
5
6
7
8
9
47 46 45 40
64 /uS
EF
TR207
TR12
BUK474
2
TR15
L20
T 2
4
3
L22
D24
C71
L25
D25
VIDEO
SUPPLAY
LINE
TR18
BU508D
LINEARITY
PIN 3
TDA8351
200 V
D 53
50 V 7
8
PIN6
TDA8351
YOKE
5 5
L26 C52
16 V C51
9
3
6
R35
10
C154
VG2
B.C.L.
PIN22
TDA8844
PIN 50
EHT P.
SERVICE
FLYBACK
PULSE TO:
PIP
TUNING
OSD SYNC
VERTICAL
YOKE
F19 VERTICAL & LINE OUTPUT
PLUS E-W CORRECTION
F19 V&HDF.DRW
E.G. 27/12/99

1 3
SCART 1
6 2
EF
CVBS & INTERCARRIER OUT
TR110
EF
TR202
TR201
TR210
6
55
2
SCART
OUT
EXT. IN
TR525
15
10
2
1
FROM PIN8
IC 100
SCART/CINCH
SWITCH
8 V
R239
F575
IC 204
TDA844X
14
12
13
AUDIO
CINCH IN
R208
SOUND
IF IN
F576
R242
1
15
IC 400 TDA2613
9 8 7 6 5 4 3 2 1
11
IC200 (2/3) HEF 4053
FROM PIN 12
IC100
SAA5297A
TR209
AUDIO OUT
TR575
F19 AUDIO MONO SIGNAL PATH
28 V
F19AMSPH.DRW
E.G. 29/12799

TDA 9870A & TDA9875A MAIN CHARACTERISTICS
FEATURES
Demodulator and decoder section
• Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF
sources SIF AGC with 24 dB control range SIF 8-bit Analog-to-Digital Converter
(ADC)
• DQPSK demodulation for different standards, simultaneously with 1-channel FM
demodulation NICAM decoding (B/G, I and L standard) Two-carrier
multistandard FM demodulation (B/G, D/K and M standard
• Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite
sound Optional AM demodulation for system L, simultaneously with NICAM
• Programmable identification (B/G, D/K and M standard) and different identification
times.
• DSP section
• Digital crossbar switch for all digital signal sources and destinations
• Control of volume, balance, contour, bass, treble,
• pseudo stereo, spatial, bass boost and soft-mute
• Plop-free volume control
• Automatic Volume Level (AVL) control
• Adaptive de-emphasis for satellite
• Programmable beeper
• Monitor selection for FM/AM DC values and signals, with peak detection option I 2 S-bus
interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and
mute.
• Analog audio section
• Analog crossbar switch with inputs for mono and stereo
E.G.Data creazione 01/11/99 17.27 23 / 30 F19MANU.doc

• (also applicable as SCART 3 input), SCART 1
• input/output, SCART 2 input/output and line output
• User defined full-level/3 dB scaling for SCART outputs
• Output selection of mono, stereo, dual A/B, dual A or Dual B
• 20 kHz bandwidth for SCART-to-SCART copies
• Standby mode with functionality for SCART copies
• Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth
15 kHz Dual audio ADC from analog inputs to DSP Two dual audio Digital-to-
Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs;
also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.
GENERAL DESCRIPTION
The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and
digital multi-channel sound systems in TV sets and satellite receivers.
Supported standards
The multistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe,
but also in Hong Kong/Peoples Republic of China and South East Asia. This includes
B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those
standard combinations otherwise only single standards are transmitted.
M standard is transmitted in Europe by the American Forces Network (AFN) with European
channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L’ standard
is normally demodulated in the 1 st sound IF. The resulting AF signal has to be entered into the
mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator
stage, however this gives limited performance. Korea has a stereo sound system similar to Europe
and is supported by the TDA9875A. Differences include deviation, modulation contents and
identification. It is based on M standard.
FUNCTIONAL DESCRIPTION
Description of the demodulator and decoder section
SIF INPUT
E.G.Data creazione 01/11/99 17.27 24 / 30 F19MANU.doc

Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner.
For higher SIF signal levels the SIF input can be attenuated with an internal switchable
10 dB resistor divider. As no specific filters are integrated, both inputs have the same
specification giving flexibility in application. The selected signal is passed through an AGC
circuit and then digitized by an 8-bit ADC operating at 24.576 MHz.
AGC
The gain of the AGC amplifier is controlled from the ADC output by means of a digital
control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC
overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation
the AGC must be switched off. When switched off, the control loop is reset and fixed gain
settings can be chosen from Table 15 (subaddress 0).
MIXER
The digitized input signal is fed to the mixers, which mix one or both input sound carriers
down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access
to the mixer control word registers is via the I 2 C-bus. When receiving NICAM programs,
a feedback signal is added to the control word of the second carrier mixer to establish a
carrier-frequency loop.
FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used
for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis
characteristic, an adaptive de-emphasis is available for encoded satellite programs. A
stereo decoder recovers the left and right signal channels from the demodulated sound
carriers. Both the European and Korean stereo systems are supported.
FM IDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of
the pilot signal and narrow-band detection of the identification frequencies. The result is
available via the I 2 C-bus interface. A selection can be made via the I 2 C-bus for B/G,
D/K and M standard and for three different modes that represent different trade-offs
between speed and reliability of identification.
NICAM DEMODULATION
The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM
demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock
signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM
E.G.Data creazione 01/11/99 17.27 25 / 30 F19MANU.doc

(pin 2). A timing loop controls the frequency of the crystal oscillator to lock the sampling
rate to the symbol timing of the NICAM data.
NICAM DECODER
The device performs all decoding functions in accordance with the “EBU NICAM 728
specification”. After locking to the frame alignment word, the data is descrambled by
applying the defined pseudo-random binary sequence; the device will then synchronize to
the periodic frame flag bit C0.
The status of the NICAM decoder can be read out from the NICAM status register by the
user. The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit
indicates that the decoder has locked to the NICAM data and that the data is valid sound
data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to
the sound conveyed by the NICAM channel. The error byte contains the number of sound
sample errors, resulting from parity checking, that occurred in the past 128 ms period.
NICAM AUTO-MUTE
This function is enabled by setting bit AMUTE LOW subaddress 14 Upper and lower error
limits may be defined by writing appropriate values to two registers in the I 2 C-bus section
(subaddresses 16 and 17; . When the number of errors in a 128 ms period exceeds the
upper error limit the auto-mute function will switch the output sound from NICAM to
whatever sound is on the first sound carrier (FM or AM). When the error count is smaller
than the lower error limit the NICAM sound is restored. The auto-mute function can be
disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the
error count increases; the user will hear a signal of degrading quality.
A decision to enable/disable the auto-muting is taken by the microcontroller based on an
interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any
additional strategy implemented by the set maker in the microcontroller software.
For NICAM L applications, it is recommended to demodulate AM sound in the first sound
IF and connect the audio signal to the mono input of the TDA9875A. By setting the AMSEL
bit subaddress 14. the auto-mute function will switch to the audio ADC instead of switching
to the first sound carrier.
CRYSTAL OSCILLATOR
The digital-controlled crystal oscillator (DCXO) is illustrated in Fig.8 (see Chapter 12). The
circuitry of the DCXO is fully integrated, only the external 24.576 MHz crystal is needed.
E.G.Data creazione 01/11/99 17.27 26 / 30 F19MANU.doc

TEST PINS
Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1
Test functions are for manufacturing tests only and are not available to customers. Without
external circuitry these pads are pulled down to LOW level with internal resistors.
POWER FAIL DETECTOR
The power fail detector monitors the internal power supply for the digital part of the device.
If the supply has temporary been lower than the specified lower limit, the power-on reset
bit POR, transmitter register subaddress 0 will be set to HIGH. The CLRPOR bit, slave
register subaddress 1 resets the power-on reset flip-flop to LOW. If this is detected, an
initialization of the TDA9875A has to be carried out to ensure reliable operation.
LEVEL SCALING
All input channels to the digital crossbar switch (except for the loudspeaker feedback path)
are equipped with a level adjust facility to change the signal level in a range of 15 dB. It
is recommended to scale all input channels to be 15 dB below full scale (15 dB full scale)
under nominal conditions.
NICAM PATH
The NICAM path has a switchable J17 de-emphasis.
FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency
offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g.
for the purpose of carrier detection. The de-emphasis function offers fixed settings for the
supported standards (50 µs, 60 µs 75 µs and J17). An adaptive de-emphasis is available
for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2
stereo, dual and mono signals.
NICAM AUTO-MUTE
If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes
poor, the digital crossbar switch switches automatically to FM and switches the matrix to
channel 1. The automatic switching depends on the NICAM bit error rate.
The auto-mute function can be disabled via the I 2 C-bus. For NICAM L applications, it is
recommended to demodulate AM sound in the first sound IF and connect the audio signal
to the mono input of the TDA9875A. By setting the AMSEL bit subaddress 14 (see Section
10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the
E.G.Data creazione 01/11/99 17.27 27 / 30 F19MANU.doc

first sound carrier. The ADC source selector subaddress 23 (see Section 10.3.20) should
be set to mono input, where the AM sound signal should be connected.
LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel
1, channel 2 and spatial effects.
There are fixed coefficient sets for spatial settings of 30%, 40% and 52%.
The Automatic Volume Level (AVL) function provides a constant output level of 23 dB full
scale for input levels between 0 and 29 dB full scale. There are some fixed decay time
constants to choose from, i.e. 2, 4 and 8 seconds.
Pseudo stereo is based on a phase shift in one channel via a 2 nd -order all-pass filter.
There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150,
200 and 300 Hz.
Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB
resolution. There is also a mute position. For the purpose of a simple control software in
the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for volume
control is identical to the volume setting in dBs (e.g. the I 2 C-bus data byte +10 sets the
new volume value to +10 dB).
Balance can be realized by independent control of the left and right channel volume
settings.
Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to
the volume setting by means of microcontroller software.
Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable
between +/-12 dB with 1 dB resolution.
For the purpose of a simple control software in the microcontroller, the decimal number
that is sent as an I 2 C-bus data byte for contour, bass or treble is identical to the new
contour, bass or treble setting in dBs (e.g. the I 2 C-bus data byte +8 sets the new value to
+8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented
coefficient set serves merely as an example on how to use this filter.
The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The
frequency can be selected via the I 2 C-bus. The beeper output signal is added to
theloudspeaker and headphone channel signals. The beeper volume is adjustable with
E.G.Data creazione 01/11/99 17.27 28 / 30 F19MANU.doc

espect to full scale between 0 and 93 dB with 3 dB resolution. The beeper is not
effected by mute.
Soft-mute provides a mute ability in addition to volume control with a well defined time (32
ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine
masking.
HEADPHONE (AUXILIARY) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel
and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled
individually for each channel in a range from +24 to 83 dB with 1 dB resolution. There is
also a mute position. For the purpose of a simple control software in the microcontroller,
the decimal number that is sent as an I 2 C-bus data byte for volume control is identical to
the volume setting in dB (e.g. the I 2 C-bus data byte +10 sets the new volume value to
+10 dB). Balance can be realized by independent control of the left and right channel
volume settings.
Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable
between +/- 12 dB with 1 dB resolution.
For the purpose of a simple control software in the microcontroller, the decimal number
that is sent as an I 2 C-bus data byte for bass or treble is identical to the new bass or
treble setting in dB (e.g. the I 2 C-bus data byte +8 sets the new value to +8 dB).
The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The
frequency can be selected via the I 2 C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals. The beeper volume is adjustable with
respect to full scale between 0 and 93 dB with 3 dB resolution. The beeper is not
effected by mute.
Soft-mute provides a mute ability in addition to volume control with a well defined time (32
ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine
masking.
SCART INPUTS
The SCART specification allows for a signal level of up to 2 V (rms). Because of signal
handling limitations, due to the 5 V supply voltage of the TDA9875A, it is necessary to
have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a +3
dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4V input),
there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line
E.G.Data creazione 01/11/99 17.27 29 / 30 F19MANU.doc

output. The input attenuator is realized by an external series resistor in combination with
the input impedance, both of which form a voltage divider. With this voltage divider the
maximum SCART signal level of 2 V (rms) is scaled down to 1.4 V (rms) at the input pin.
EXTERNAL AND MONO INPUTS
The 3 dB input attenuators are not required for the external and mono inputs, because
those signal levels are under control of the TV designer. The maximum allowed input level
is 1.4 V (rms). By adding external series resistors, the external inputs can be used as an
additional SCART input.
SCART OUTPUTS
The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3
dB or to 0 dB via the I 2 C-bus. The +3 dB position is needed to compensate for the 3 dB
attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be
preferred [under the condition of 1.4 V (rms) maximum input level]. The 0 dB position is
needed, for example, for an external-to-SCART copy with 0 dB gain.
LINE OUTPUT
The line output can provide an unprocessed copy of the audio signal in the loudspeaker
channels. This can be either an external signal that comes from the dual audio ADC, or a
signal from an internal digital audio source that comes from the dual audio DAC. The line
output employs amplifiers with two gain settings. The +3 dB position is needed to
compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for
example, for non-attenuated external or internal digital signals (see Section 6.3.4).
E.G.Data creazione 01/11/99 17.27 30 / 30 F19MANU.doc

TO PIN 9 IC1
TDA9811
TR8
INTERCARRIER
EF
FROM PIN 20 IC1
TDA9811
6 V
TO L/L' FILTER
SWITCH
TR8
AM AUDIO
FROM PIN 22 IC1
TDA9811
II S
IIC BUS
STD SWITCH
TR6
EF
L /L' SWITCH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PLCK
NICAM
ADDR1
SCL
SDA
VSSA1
VDEC1
Iref
P1
SIF2
Vref
SIF1
ADDR2
Vssd1
Vdd1
CRESET
Vssd4
XTAL1
XTAL0
P2
SYSLCK
SCK
WS
SDO2
SDO1
SDI2
SDI1
TEST1
MONOIN
TEST2
EXT/R
EXT/L
IIC
IN / OUT
IDENT
I / O
PORT
PEAK
DETEC.
VCXO
CLOCK
IIS
ENC.
DEC.
FM DEM
(AM DEM)
DEMATR
DEEMPH
LEVEL
ADJ.
CHANNEL
SELECTION
QPSK
DEM.
NICAM
DEC.
LEVEL
ADJ.
AUDIO PROCESSING
L.S.
AVL,VOL
CONTOUR
BASS
TREBLE
PSEUDO
BASS CORR
DAC
INPUT SWITCH
AGC ADC
DAC
DAC
H.P.
VOL.
BASS
TREB.
DAC
TDA9875A
ANALOGUE CROSS BAR SWITCH
TEST
VDD2
LOR
LOL
MOL
MOR
Vdda
AUXOL
AUXOR
Vssa3
pcapl
pcapr
vREF3
SCOL2
SCOR2
Vssa4
Vssd2
SCOL1
SCOR2
Vref2
i.c.
i.c.
Vssa2
i.c.
i.c.
Vref(n)
Vref(p)
Vdec2
SCIL2
SCIR2
Vssd3
SCIL1
SCIR1
TDA9875A PINOUT & PERIPHERALS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AUDIO LINE OUT
6 V
TR11
TR12
TR9
AUDIO OUT TO SCART
AUDIO FROM SCART
6 V
TO AUDIO
AMPLIFIER
TR10
TO HEADPHONES
APLIFIER
IC4
TDA2822M
TDA9875A.DRW
E.G. 7/11/99

TDA9811
Multistandard VIF-PLL
with QSS-IF and AM demodulator
FEATURES
• 5 V supply voltage
• Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled)
• True synchronous demodulation with active carrier regeneration (very linear
demodulation, good intermodulation figures, reduced harmonics, excellent pulse
response)
• Gated phase detector for L/L accent standard VCO frequency switchable between L
and L accent (alignment external) picture carrier frequency
• Separate video amplifier for sound trap buffering with high video bandwidth VIF AGC
detector for gain control, operating as peak sync detector for B/G (optional external
AGC) and peak white detector for L; signal controlled reaction time for L
• Tuner AGC with adjustable takeover point (TOP)
• AFC detector without extra reference circuit
• SIF input for single reference QSS mode (PLL controlled); SIF AGC detector for gain
controlled SIF amplifier; single reference QSS mixer able to operate in high
performance single reference QSS mode
• AM demodulator without extra reference circuit
• AM mute (especially for NICAM)
• Stabilizer circuit for ripple rejection and to achieve constant output signals.
GENERAL DESCRIPTION
The TDA9811 is an integrated circuit for multistandard vision IF signal processing and
sound AM demodulation, with single reference QSS-IF in TV and VCR sets.
TDA9811 QSS Pagina 1 di 4 e.g. TDA9811R

h
VIF input switch
TOP
tuner
AGC
loop
filter
2 x f PC
AFC
30 28 3 6
19
7
25
24
23
TUNER AND VIF-AGC
VCO TWD
AFC DETECTOR
VIFB
VIFA
SIF
5
4
2
1
32
31
VIF AMPLIFIER
AND
INPUT SWITCH
SIF
AMPLIFIER
FPLL
SINGLE REFERENCE
MIXER AND
AM DEMODULATOR
VIDEO DEMODULATOR
AND AMPLIFIER
TDA9811
VIDEO
BUFFER
AF AMPLIFIER
AND SWITCH
21
10
22
12
video
1 V (p-p)
CVBS
2 V (p-p)
V i(vid)
AF/AM
INTERNAL VOLTAGE
STABILIZER
SIF-AGC
29 27 26 9 8
20 11 18 16 15 17
13
14
n.c.
n.c.
1/2 V P
5 V
standard
switch
CAGC
C AGC C BL
MHA046
(2nd SIF)
V o QSS
L′/L
switch
n.c.
n.c.
n.c.
mute switch, AM

FUNCTIONAL DESCRIPTION
Vision IF amplifier and input switch The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage comprises a feedback network
controlled by emitterdegeneration. T
The first differential stage is extended by two pairs of emitter followers to provide two IF
input channels. The VIF input can be selected by pin 30
Tuner and VIF AGC
The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the
tuner AGC to generate the tuner AGC output current (open-collector output).
The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to
be matched to achieve the optimum IF input level.
The AGC detector charges/discharges the AGC capacitorto the required voltage for setting
of VIF and tuner gain in order to keep the video signal at a constant level.
Therefore for negative video modulation the sync level and for positive video modulation
the peak white level of the video signal is detected. In order to reduce the reaction
time for positive modulation, where a very large time constant is needed, an additional
level detector increases the discharging current of the AGC capacitor (fast mode)
in the event of a decreasing VIF amplitude step. The additional level information is given
by the black-level detector voltage.
Frequency Phase Locked Loop detector (FPLL)
The VIF-amplifier output signal is fed into a frequency detector and into a phase detector
via a limiting amplifier.
During acquisition the frequency detector produces a DC current proportional to the
frequency difference between the input and the VCO signal. After frequency lock-in the
phase detector produces a DC current proportional to the phase difference between the
VCO and the input signal. The DC current of either frequency detector or phase detector is
converted into a DC voltage via the loop filter, which controls the VCO frequency. In the
event of positive modulated signals the phase detector is gated by composite sync in order
to avoid signal distortion for overmodulated VIF signals.
TDA9811 QSS Pagina 2 di 4 e.g. TDA9811R

VCO, Travelling Wave Divider (TWD) and AFC
The VCO operates with a resonance circuit (with L and C in parallel) at double the PC
frequency. The VCO is controlled by two integrated variable capacitors.
The control voltage required to tune the VCO from its free-running frequency to actually
double the PC frequency is generated by the frequency-phase detector and fed via the
loop filter to the first variable capacitor (FPLL). This control voltage is amplified and
additionally converted into a current which represents the AFC output signal. The VCO
centre frequency can be decreased (required for L accent standard) by activating an
additional internal capacitor. This is achieved by using the L accent switch. In this event
the second variable capacitor can be controlled by a variable resistor at the L accent
switch for setting the VCO centre frequency to the required L accent value. At centre
frequency the AFC output current is equal to zero.
The oscillator signal is divided-by-two with a TWD which generates two differential output
signals with a 90 degree phase difference independent of the frequency.
Video demodulator and amplifier
The video demodulator is realized by a multiplier which is designed for low distortion and
large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the
travelling wave divider output. In the demodulator stage the video signal polarity can be
switched in accordancewith the TV standard. The demodulator output signal is fed via an
integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The
video amplifier is realized by an operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics
for B/G and L standard. The standard dependent level shift in this stage delivers the same
sync level for positive and negative modulation. The video output signal is 1 V (p-p) for
nominal vision IF modulation.
Video buffer
For an easy adaption of the sound traps an operational amplifier with internal feedback is
used in the event of B/G and L standard. This amplifier is featured with a high bandwidth
and 7 dB gain. The input impedance is adapted output stage delivers a nominal 2 V (p-p)
positive video signal. Noise clipping is provided.
TDA9811 QSS Pagina 3 di 4 e.g. TDA9811R

SIF amplifier and AGC
The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each
differential stage comprises a controlled feedback network provided by emitter
degeneration. The SIF AGC detector is related to the SIF input signals (average level of
AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the
AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to
‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC
is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is
also set to ‘fast’ controlled by the standard switch.
Single reference QSS mixer The single reference QSS mixer is realized by a multiplier.
The SIF amplifier output signal is fed to the single reference QSS mixer and converted to
intercarrier frequency by the regenerated picture carrier (VCO).
The mixer output signal is fed via a high-pass for attenuation of the video signal
components to the output pin 20. With this system a high performance hi-fi stereo
sound processing can be achieved.
AM demodulator
The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal
is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The
demodulator output signal is fed via an integrated low-pass filter for attenuation of the
carrier harmonics to the AF amplifier.
Internal voltage stabilizer and 1 ¤2 VP -reference
The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of
supply voltage and temperature. A voltage regulator circuit, connected to this voltage,
produces a constant voltage of 3.6 V which is used as an internal reference voltage.
For all audio output signals the constant reference voltage cannot be used because large
output signals are required.
TDA9811 QSS Pagina 4 di 4 e.g. TDA9811R

PINNING
SYMBOL PIN DESCRIPTION
V i VIF1 1 VIF differential input signal voltage 1
V i VIF2 2 VIF differential input signal voltage 2
C BL 3 black level detector
V i VIF3 4 VIF differential input signal voltage 3
andbook, halfpage
Vi VIF1
1
32
Vi SIF2
V i VIF4 5 VIF differential input signal voltage 4
Vi VIF2
2
31
Vi SIF1
TADJ 6 tuner AGC takeover adjust (TOP)
T PLL 7 PLL loop filter
C SAGC 8 SIF AGC capacitor
STD 9 standard switch
V o CVBS 10 CVBS output signal voltage
LSWI 11 L/L accent switch
CBL
Vi VIF3
V i VIF4
TADJ
TPLL
3
4
5
6
7
30
29
28
27
26
INSWI
VP
CVAGC
GND
Cref
V oAF 12 AM audio voltage frequency output
n.c. 13 not connected
CSAGC
STD
8
9
TDA9811
25
24
VCO2
VCO1
n.c. 14 not connected
n.c. 15 not connected
n.c. 16 not connected
MUTE 17 AM mute
n.c. 18 not connected
Vo CVBS
LSWI
Vo AF
n.c.
10
11
12
13
23
22
21
20
AFC
Vi(vid)
Vo(vid)
Vo QSS
TAGC 19 tuner AGC output
n.c.
14
19
TAGC
V o QSS 20 single reference QSS output voltage
n.c.
15
18
n.c.
V o(vid) 21 composite video output voltage
n.c.
16
17
MUTE
V i(vid) 22 video buffer input voltage
AFC 23 AFC output
MHA047
VCO1 24 VCO1 reference circuit for 2f PC
VCO2 25 VCO2 reference circuit for 2f PC
C ref 26 1 ⁄ 2 V P reference capacitor
GND 27 ground
C VAGC 28 VIF AGC capacitor
V P 29 supply voltage
INSWI 30 VIF input switch
V i SIF1 31 SIF differential input signal voltage 1
V i SIF2 32 SIF differential input signal voltage 2
Fig.2 Pin configuration.

TDA9830
TV sound AM-demodulator and
audio source switch
FEATURES
• Adjustment free wideband synchronous AM demodulator
• Audio source-mute switch (low noise)
• Audio level according EN50049
• 5 to 8 V power supply or 12 V alternative
• Low power consumption.
GENERAL DESCRIPTION
The TDA9830, a monolithic integrated circuit, is designed for AM-sound demodulation
used in L- and L’-standard.
The IC provides an audio source selector and also mute switch.
FUNCTIONAL DESCRIPTION
Sound IF input
The sound IF amplifier consists of three AC-coupled differential amplifier stages each with
approximately 20 dB gain. At the output of each stage is a multiplier for gain controlling
(→ current distribution gain control). The overall control range is approximately -6 to +60
dB and the frequency response (-3 dB) of the IF amplifier is approximately 6 to 70 MHz.
The steepness of gain control is approximately 10 mV/dB.
IF AGC
The automatic gain control voltage to maintain the AM demodulator output signal at a
constant level is generated by a mean level detector. This AGC-detector charges and
discharges the capacitor at pin 3 controlled by the output signal of the AM-demodulator
compared to an internal reference voltage. The maximum charge/discharge current is
approximately 5 mA. This value in combination with the value of the AGC capacitor and
the AGC steepness determines the lower cut-off audio frequency and the THD-figure at
low modulation frequency of the whole AM-demodulator. Therefore a large time constant
has to be chosen which leads to slow AGC reaction at IF level change. To speed up the
AGC in case of IF signal jump from low to high level, there is an additional comparator built
in, which can provide additional discharge current from the AGC capacitor up to 5 mA in a
case of overloading the AM demodulator by the internal IF signal.
AM-demodulator
The IF amplifier output signal is fed to a limiting amplifier (two stages) and to a multiplier
circuit. However the limiter output signal (which is not any more AM modulated) is also fed
to the multiplier, which provides AM demodulation (in phase demodulation). After lowpass
filtering (fg ≈ 400 kHz) for carrier rejection and buffering, the demodulator output signal is
present at pin 6. The AM demodulator operates over a wide frequency range, so that in

combination with the frequency response of the IF amplifier applications in a frequency
range from approximately 6 MHz up to 70 MHz are possible.
Audio switch
This circuit is an operational amplifier with three input stages and internal feedback
network determining gain (0 dB) and frequency response (fg ≈ 700 kHz). Two of the input
stages are connected to pin 7 and pin 9, the third input stage to an internal reference
voltage. Controlled by the switching pins 10 and 12, one of the three input stages can be
activated and a choice made between two different AF signals or mute state. The selected
signal is present at pin 8. The decoupling capacitors at the input pins are needed, because
the internally generated bias voltage for the input stages must not be influenced by the
application in order to avoid DC-plop in case of switching.
The AM demodulator output is designed to provide almost the same DC voltage as the
input bias voltage of the audio switch. But there may be spread between both voltages.
Therefore it is possible to connect pin 6 directly to pin 7 (without a decoupling capacitor),
but in this event the DC-plop for switching can increase up to 100 mV.
Reference circuit
This circuit is a band gap stabilizer in combination with a voltage regulation amplifier,
which provides an internal reference voltage of about 3.6 V nearly independent from
supply voltage and temperature. This reference voltage is filtered by the capacitor at pin 4
in order to reduce noise. It is used as a reference to generate all important voltages and
currents of the circuit. For application in 12 V power supply concepts, there is an internal
voltage divider in combination with a Darlington transistor in order to reduce the supply
voltage for all IC function blocks to approximately 6 V.
This is necessary because of use of modern high frequency IC technology, where most of
the used integrated components are only allowed to operate at maximum 9 V supply
voltage.

A1
INTERCARRIER INPUT
MONO
INPUT
12 7 6 8 11 10 9 5
IIC
SCL
SDA
10
12
4
5
6V
INPUT
SWITCH
AGC
ADC
IIC
3IIC ADDRES.
6 7 8
VSSA1
29 31 32 33 34 35 36 37 38 39
47 48
TDA9870A
FM DEM
(AM DEM)
IDENT
F19
STEREO A2
MODULE
ANALOGUE CROSS BAR SWITCH
I / O
PORT
EXT. IN
SCART OUT
2 1 4 3
DEMATR
DEEMPH
PEAK
DETECT.
LEVEL
ADJ.
VCXO
CLOCK
DAC
DAC
CHANNEL
SELECTION
IIS
IIS
ENC / DEC.
2° IIC ADDRESS 18 19
17 14 20 9 11 13 15 16 21 22 23 24 25 26 27
6 V
A3
SCART SOUND OUT
49 50 59 64
51 52 62 63
IIS
F19STA2 .DRV
E.G 5/11/99
LINE OUT
AUDIO
PROCESSING
L.S .
AVL, VOL
CONTOUR, BASS
TREB, PSEU
BASSCORR
BEEPER
H.P.
VOL, BEEP.
BASS, TREB.
VDDA3 VDDD2
VSSD2 49
VSSA2 43
VSSA3 56
VSSA4 50
TEST
DAC
DAC
28
30
57
58
60
61
TR10
6 V
26V
TR9
TR12
TR11
IIC
7 6
HEADPHONES
IC 4 AMPLIFIER
TDA2822M
2 4
KIA7812
1
2 3 12 V
IC 5
A2
1
3
1
2
3
4
7
10
8
9
5
6

IF IN
F19NICAM.DRV
E.G 5/11/99
7 5 12 6 8 11 10 9
TR6
EF
12 V
TR1
EF
IIC
R5
6V
R6
SCL
SDA
TR5
EF
D1
TDA9875A
10
12
1
PLK
2
4
5
6V
INPUT
SWITCH
AGC
ADC
NICAM
DATA
IIC
3 IIC ADDR.
6 7 8
TR2
TR4
R7
12V
STEREO INTERCARRIER ONLY
R6
D2
L /L'
29 31 32 33 34
QPSK
DEM.
FM DEM
(AM DEM)
IDENT
ANALOGUE CROSS BAR SWITCH
I / O
PORT
NICAM
DEC.
DEMATR
DEEMPH
PEAK
DETECT.
35 36 37 38 39
47 48
LEVEL
ADJ.
LEVEL
ADJ.
VCXO
CLOCK
DAC
DAC
CHANNEL
SELECTION
IIS
IIS
ENC / DEC.
2° IIC ADDRESS 18 19
22 23
17 14 20 9 11 13 15 16 21
24 25 26 27
TR3
2
1
FOS2
FOS 1
3
EXT. IN
TR8
8V
2 1 4 3
1
2
4
5
31
32
30 VIF SWT. 9
IF AMPL.
&
VIDEO
SWITCH
STD
6 V
IIS
28 3 6 19
TUNER & VIF AGC
SIF
AMPL.
FPLL
TDA 9811 29 27
IC 1
5 V
A1
A3
SCART SOUND OUT
49 50 59 64
51 52 62 63
VDDA3 VDDD2
VSSD2 49
L/L'
R20
11
FM MIXER
& AM DEM.
20
AUDIO
PROCESSING
L.S .
AVL, VOL
CONTOUR, BASS
TREB, PSEU
BASSCORR
BEEPER
H.P.
VOL, BEEP.
BASS, TREB.
TR7
VCO
L1
24 25
VIDEO
DEMOD.
23
AF AMPL.
& SWT.
8 V
AFC
12
VSSA2 43
VSSA3 56
VSSA4 50
TEST
DAC
DAC
21
10
22
17
MUTE
28
30
57
58
60
61
TR10
6 V
TR9
TR12
TR11
7 6
HEADPHONES
AMPLIFIER
IC 4 TDA2822M
2 4
12 V
3
KIA7812
1 2
26 V
26V
IC 5
FROM
PIM 7
A2
IIC
A2
F19
NICAM
MODULE
1
3
1
2
3
4
7
10
8
9
5
6

STEREO MODULE CONNECTOR
3 4
7
1 2 8 9
IC 400 TDA1521A
9 8 7 6 5 4 3 2 1
1
FROM PIN 11
TUNER (I.F.)
3
2
6
19
4
FROM PIN 6 IC 100
AV1 / AV2
SWITCH
20
TR110
FROM PIN8
IC 100
SCART/CINCH
SWITCH
SCART 1
18
17
16
15
10
2
12
11
1
13
14
15
14
12
13
AUDIO
CINCH IN
8
11
F19ASSPH.DRW
E.G. 29/12799
FROM PIN 7 IC 100
TV/AV SWITCH
TO AV2
SCART 2
IC201 (2/3 OF LA7955)
6 2 1 3
IC200 (2/3) HEF 4053
F19 AUDIO STEREO SIGNAL PATH

TDA4605
Control IC for Switched-Mode Power Supplies
using MOS-Transistors
Features
• Fold-back characteristic provides overload protection for external components
• Burst operation under short-circuit conditions
• Loop error protection
• Switch-off if line voltage is too low (undervoltage switch-off)
• Line voltage compensation of overload point
• Soft-start for quiet start-up
• Chip-over temperature protection (thermal shutdown)
• On-chip parasitic transformer oscillation suppression circuitry
Functional desciption
The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary
regulation and monitoring functions in free running flyback converters. Since good load
regulation over a wide load range is attained, this IC is applicable tor consumer and
industrial power supplies.
The serial circuit of power transistor and primary winding of the flyback transformer is
connected to the input voltage. During the switch - on period of the transistor, energy is
stored in the transformer and during the switch - off period it is fed to the load via the
secondary winding. By varying switch-ontime of the power transistor, the IC controls each
portion of energy transferred to the secondary side such that the output voltage remains
nearly independent ot load variations.
The required control information is taken from the input voltage during the switch-on period
and from a regulation winding during the switch-off period.
In the different load ranges the switched-mode power supply (SMPS) behaves as follow:
TDA4605 SMPS CONTRO I.C. Pagina 1 di 6
e.g.tda4605R.doc

No load operation:
The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz.
Depending upon
the transformator windings the output voltage can be slightly above nominal value.
Nominal operation:
The switching frequency declines with increasing load and decreasing AC-voltage. The
duty factor primarly depends on the AC-voltage. The output voltage is load-dependent
only.
Overload point:
Maximal output power is available at this point ot the output characteristic.
Overload:
The energy transferred per operation cycle is limited at the top. Therefore the output
voltage declines by secondary overloading..Semiconductor Group 35
TDA 4605 Pin Definitions and Functions
Pin No. Function
1 Regulating Voltage: Information input concerning secondary voltage. By
comparing the regulating voltage - obtained from the regulating winding ot the transformer
- with the internal reference voltage, the output impulse width on pin 5is adapted to the
load ot the secondary side (normal, overload, short-circuit, no load).
2 Primary Current Simulation: Information input regarding the primary current.
The primary current rise in the primary winding is simulated at pin 2 as a voltagerise by
means ot external RC-element. When a value is reached that is derivedfrom the regulating
voltage at pin 1, the output impulse at pin 5 is terminated. TheRC-element serves to set
the maximum power at the overload point set.
3 Input for Primary Voltage Monitoring: In the normal operation V 3 is moving
between the thresholds V 3H and V 3L (V 3H > V 3 > V 3L ). V 3 < V 3L : SMPS is
switched OFF (line voltage too low). V 3 > V 3H : Compensation of the overload point
regulation (controlled by pin 2) starts at V 3H : V 3L = 1.7.
TDA4605 SMPS CONTRO I.C. Pagina 2 di 6
e.g.tda4605R.doc

4 Ground
5 Output: Push-pull-output provides 1 A for rapid charge and discharge of the
gate capacitance ot the power MOS-transistor.
5 Supply Voltage Input: A stable internal reference voltage V REF is derived from
the supply voltage also the switching thresholds V 6A , V 6E , V 6 max and V 6 min for the
supply voltage detector. If V 6 > V 6E then V REF is switched on and swiched off when V
6 < V 6A . In addition the logic is only enable for V 6 min < V 6 < V 6 max .
7 Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
8 Zero Detector: Input tor the oscillation feedback. After starting oscillation, every
zero transit of the feedback voltage (falling edge) triggers an output impulse at
pin 5. The trigger threshold is at + 50 mV typical..Semiconductor Group 36
TDA 4605 Application Circuit
Application circuit shows a flyback converter for video recorders with a power rating of 50
W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270
V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C 1 . The
NTC limits the rush in current.In the period before the switch-on threshold is reached the
IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C 2 ,
under steady-state conditions the IC receives its supply voltage from transformer winding n
1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel-connected capacitor C 3 and the inductance ot primary winding 112 determine
the system resonance frequency. The R 2 - C 4 - D2 circuitry limits overshoot peaks, and
R 3 protects the gate of T1 against static charges.
While T1 conducts, the current rise in the primary winding depends on the winding’s
inductance and the V C1 voltage. A voltage reproduction ot the current rise is tabbed using
the R 4 - C 5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5
must be dimensioned correctly in order to prevent driving the transformer core into
saturation.
The R 10 /R 11 divider ratio provides the line voltage threshold controlling the
undervoltage control circuit in the IC. The voltage present at pin 3 also determines the
overload. Detection of overload together with the current characteristic at pin 2 controls the
on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages.
TDA4605 SMPS CONTRO I.C. Pagina 3 di 6
e.g.tda4605R.doc

Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In
addition the logic is disabled in the event of low voltage by comparison with the internal
stable voltage V V in the primary voltage monitor block.
Pin 4 Ground
Pin 5 In the output stage the output signals produced by the logic are shifted to a leved
suitable for MOS-power transistors.
Pin 6 From the supply voltage V 6 are derived a stable internal reference V REF and the
switching threshold V 6A , V 6E , V 6 max and V 6 min for the supply voltage monitor. All
reference values (V R , V 2B , V ST ) are derived from V REF . If V 6 > V VE the V REF is
switched on and switched off when V 6 < V 6A . In addition, the logic is released only for V
6 min < V 6 < V 6 max .
Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output
causes a reductio in maximal impulse duration. This function can be used to implement a
soft start, when pin 7 is connected to ground by a capacitor
Pin 8 The zero detector controlling the logic block recognizes the transformer being
discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for
a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new
pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time
t UL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50
for a line voltage barely above the lower acceptable limit voltage value (without soft-start).
After applying the line voltage at the time t 0 to the tollowing voltages built up:
– V 6 corresponding to the half-wave charge current over R 1
– V 2 to V 2 max (typically 6.6 V)
– V 3 to the value determined by the divider R 10 /R 11 .
The current drawn by the IC in this case is less than 1.6 mA. If V 6 reaches the threshold V
6E (time point t 1 ), the IC switches on the internal reference voltage. The currentdraw
max. rises to 12 mA.
The primary current- voltage reproducer regulates V 2 down to V 2E and the starting
impulse generator generates the starting impulses from time point t 5 to t 6 . The feedback
to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
TDA4605 SMPS CONTRO I.C. Pagina 5 di 6
e.g.tda4605R.doc

controlled in width by regulating voltage of pin 1. When switching on this corresponds to a
short-circuit event, i.e. V 1 = 0.
Hence the IC starts up with "short-circuit impulses" to assume a width depending on the
regulating voltage feedback (the IC operates in the overload range). The maximum pulse
width is reached at time point t 2 (V 2 = V 2 max ). The IC operates at the overload point.
Thereafter the peak values ot V 2 decrease rapidly, as the IC is operating within the
regulation range. The regulating loop has built up. If voltage V 6 falls below the switch-off
threshold V 6 min before the reversal point is reached, the starting attempt is aborted (pin
5 is switched to low). As the IC remains switched on, V 6 further decreases to V 6 . The IC
switches off; V 6 can rise again (time point 14) and a new start-up attempt begins at time
point t 1 . If the rectified alternating line voltage (primary voltage) collapses during load, V
3 can fall below V 3A , as is happening at time point t 3 (switch-on attempt when voltage is
too low). The primary voltage monitor then clamps V 3 to V 3S until the IC switches off (V
6 < V 6A ). Then a new start-up attempt begins at time point t
Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1
typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses
(V 5 = H). The peak voltage value at pin 2 increases up to V 2S max . If the secondary
load is further increased, the overload amplifier begins to regulate the pulse width
downward. This point is referred to as the overload point of the power supply. As the IC
supply voltage V 6 is directly proportional to the secondary voltage, it goes down in
accordance with the overload regulation behaviour. If V 6 falls below the value V 6 min ,
the IC goes into burst operation. As the time constant of the half-wave charge-up is
relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width t pk . This pulse width must remain possible, in order to permit the IC to
start-up without problems from the virtual short circuit, which every switching on with V 1 =
0 represents. If the secondary side is unloaded, the loading impulses (V 5 = H) become
shorter. The frequency increases up to the resonance frequency of the system. If the load
is further reduced, the secondary voltages and V 6 increase. When V 6 = V 6 max , the
logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe
under no-load conditions.
TDA4605 SMPS CONTRO I.C. Pagina 6 di 6
e.g.tda4605R.doc

Regulation of the switched-mode power supply is via pin 1. The control voltage of winding
n 1 during the off-period of T1 is rectified by D3, smoothed by C 6 and stepped down at an
adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C 7 network suppresses parasitic
overshoots (transformer oscillation).
The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that
the voltage applied across the control winding, and hence the output voltages, are at the
desired level.
When the transformer has supplied its energy to the load, the control voltage passes
through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero
crossings are also produced by transformer oscillation after T1 has turned off if output is
short-circuited. Thereforethe IC ignores zero crossings occurring within a specitied period
of time after T1 turn-off.
The capacitor C 8 connected to pin 7 causes the power supply to be started with shorter
pulses to keep the operating ftrequency outside the audible range during start-up.
On the secondary side, tive output voltages are produced across winding n 3 to n 7
rectified by D4 to D8 and smoothed by C 9 to C 13 . Resistors R 12 , R 14 and R 19 to R
21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output
circuits, which are designed to supply only small loads..
TDA 4605 Block Diagram
Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal
reference voltage V R in the regulating and overload amplifier. The output of this stage
is ted to the stop comparator.
Pin 2 A voltage proportional to the drain current ot the switching transistor is generated
there by theexternal RC-combination in conjunction with the primary current transducer.
The output of this transducer is controlled by the logic and referenced to the internal stable
voltage V 2B . If the voltage V 2 exceeds the output voltage of the regulating amplifier, the
logic is reset by the stop comparator and consequently the output ot pin 5 is switched to
low potential. Further inputs tor the logic stage are the output for the start impulse
generator with the stable reference potential V ST and the supply voltage monitor.
TDA4605 SMPS CONTRO I.C. Pagina 4 di 6
e.g.tda4605R.doc

MAINS
INPUT
NON MAINS ISOLATED SECTOR
F 19
S.M.P.S.
(CONFIGURATION WITHOUT
ZERO POWER STAND BY MODULE)
line output stage
START-UP
R1
DRIVE
OUTPUT
PULSE
5
6
D13
SOFTSTART
4 3 2
7 8
SMPS CONTROL
IC1 TDA 4605
PRIMARY
VOLTAGE & CURRENT
SENSING
D6
1
TR 1
STH7N80FI
ZERO CROSSING
DETECTOR
R14
D8
SUPPLY VOLTAGE
ADJUSTMENT
OVER LOAD
PROTECTION
15
3
11
9
T 1
8
2
4
10
6 / 16
12
148 V (110°)
128 V
5
2
1
FROM PIN 19OFF
IC 100
SAA5297A ON
TR 2
4
8
9
TR3
TR 4
8,5v
TR5
26 V
sound
power
line driver
26 V
12 V
signal
processing
stand by
5 V
5 V
F19SMPS.DRW
E.G. 7/11/99
TR6

15
3
2
4
10
148 V (110°)
128 V
TR3
TR 4
26 V
sound
power
line driver
26 V
line output stage
F 19
LOW POWER
STAND-BY
CONFIGURATION
11
8
IC10
5
8
2 TDA8183
1 4 9
12 V
signal
processing
5 V
stand by
9
T 1
6 / 16
12
8,5v
ON
OFF
5 V
FROM PIN 19
IC 100
SAA5297A
TR 2
MAINS TO MAIN BOARD
1
T1
9
IC2 IL410
TR2 BT808
FROM
MAINS
SWITCH
7
1
IC 1
L7805CV
2
3
X1
A12
ON-OFF
5
STAND-BY MODULE
X2
X3
5 V ST-BY
F19LPSBC.DRW
E.G. 14 /11/99

F19
SERVICE MODE

For the description of the use of the TV make use of the Instruction Manual
Service mode
As already mentioned in the summary the remote control can be used to set all
parameter and to adjust the TV set without to open the back cover.
There are two ways to enter the "SERVICE MODE" that are to use the LOCAL
KEYBOARD or to have a precial prepared REMOTE CONTROL.
FIRST METHOD. (If the special remote control is available use the button following the
indication of the Table 1
Table 1 List of command of the "SERVICE REMOTE CONTROL"
BUTTON RC5 Sub Decimal Coce
System
0 0 0 Vertical Slope
Function
1 0 1 Vertical Amplitude
2 0 2 Vertical Shift
3 0 3 Vertical S Correctio
4 0 4 Horizontal Shift
5 0 5 HorizontalAmplitude
6 0 6 E-W parabola
7 0 7 E-W Corner
8 0 8 E-W Trapezium
9 0 9 AGC
Pr + 0 32 Up Carousel of all Service Parameter
Pr - 0 33 Down Carousel of all Service Parameter
Vol + 0 16 Adjust Parameter Value (UP)
Vol - 0 17 Adjust Parameter Value (Down)
TV 0 63 Leave SERVICE MODE" without to store
MEM 0 50 Leave SERVICE MODE with store
MENU 0 53 Wred
SERVICE 7 58 SERVICE MODE ENTER
E.G.Data creazione 31/10/99 15.38 3 / 7 f19intro

Table 2 Parameter and value to be adjusted in "SERVICE MODE"
PARAMETER VALUE DESCRIPTION
init ctvfor v0.6 on/ off Default Initialization
vg2test on/off Cut -off adjustment
txtbri 0--63 Adjust TXT brightness
txtcon 0--63 Adjust TXT Contrast
884c04 Bit (FSU) Increase blue stretch and the dynamic skin
884c03 Bit (FSU) Adj. acl (automatic colour limiter - and cathode drive level.
88c02 Bit (FSU) Adj.(black stretch), blue stretch, and the blue back
optionb1 Bit (FSU) Select TV standard and TXT character set
optionb2 Bit (FSU) Scart type selections (
optionb3 Bit (FSU) (*) Hotel mode setting
nicamuperror 0--63 Nicam sensitivity (upper limit)
nicamlowerror 0--63 Nicam sensitivity (Lower limit).
nicamcon Bit (FSU) Tda9875 CONTROL
pipcontrast 0--15 PIP Contrast control
wblue 0--63 Blue channel gain
wgreen 0--63 “Green channel gain
wred 0--63 “Red channel gain
ydelaypal 0--63 Luma chroma delay
ewtrapeze 0--63 E-W- Trapezium adjustment
ewcorner 0--63 E-W- Corner Adjustment
ewparab 0--63 E-W- Parabola Adjustment
ewwidth 0--63 Horizontal Amplitude
h-shift 0--63 Horizontal shift
s-corr 0--63 Vertical S-Correction
v-shift 0--63 Shift Vertical
v-ampl 0--63 Vertical Amplitude
v-slope 0--63 Slope Vertical
agc 0--63 AGC adjustment
if xx afc 2/3 0--63 (FSU) Factory set up
LEGENDA: (FSU)= FACTORY SET UP
(*) REDUCE OF A QUANITY 4 TO GET HOTEL MODE
WARNING!! Do not change value for those parameter that are highlighted please
E.G.Data creazione 31/10/99 15.38 5 / 7 f19intro

Note 1
If during the installation of the TV set the AUTOSTORE" method is used, it is
fundamental, before to start the function, to select the name of the country as the criteria of
listing the broadcasters names is fixed by EBU table that are related to the country itself. It
is possible to find more channels of the same broadcaster on the Arial. In this case the
system will place first the signal having TXT with the strongest signal level than the others
and finally, with the found sequence the weakest one without TXT.
Note 2
To get HOTEL MODE it is necessary to enter "SERVICE MODE" and to change the
parameter "optionb3". Read the original value e subtract 4 (decimal). In HOTEL MODE all
tuning systems are not possible, the volume is pre fixed and the MENU from the LOCAL
KEY BOARD is not accessible.
Note 3
For fast programming (in case of installation of several TV set in Shops or Hotels a
"Black Box" is available on request. The procedure for a quick program is as follows:
1. Install and tune all channel storing it in the program sequence you want
2. Switch off the Set with the remote control and leave it in Stand-by mode
3. Switch on the "Black Box" and connect it to Scart
4. Press the button corresponding to the chassis to be programmed and at the same time
press the button "Read" for a while. (corresponding LED will be on.
5. When the LED "Write" became off (after few seconds) disconnect the "Black Box"
6. Insert the Black Box in the new TV set (in stand by condition)
7. Press F19 and "Write" buttons at same time. Corresponding "Write" LED will light
8. After few seconds when the "Write" LED will switch-off the procedure is finished .
9. Repeat points from 6 to 8 to program others TV set
WARNING!!!!! The above procedure can be applied
only to TV set specially prepared for this functions
E.G.Data creazione 31/10/99 15.38 6 / 7 f19intro

Table 4 List of languages that can be reproduced as a function of the TXT characters set
setting with the optionb1 (bit number 6)
WEST EUROPE CHARACTER SET
LANGUAGES
EAST EUROPE CHARACTER SET
LANGUAGES
ENGLISH
POLISH
GERMAN
GERMAN
SWEDISH
ESTONIA
ITALIAN
SERB-CROAT
FRENCH
CZECH
SPANISH
RUMEN
TURKISH
Just to give an example how to set the option byte 1, 2, and 3 we can start from
a TV set for BG standard, with hyperband tuner to be sold in a country using West
European character set.
Locking at the table 3 Optionb1 we have the following condition:
BIT
OPTIONB1
NUMBER 0 1 VALUE WEIGHT
0 BG 1 1
1 L/L' 0
2 I 0
3 DK 0
4 X 0
5 X 0
6 E.E.TXT W.E. TXT 1 64
7 CATV 1 128
Adding the value of the
last column we get 193
in decimal form and C!
in hexadecimal.
This means that we
have to choose this
value (C1) for the
optionb1 in service
mode
If we want to change from West Europe character set to East Europe, bit 6
became 0 that is the new value is 129 (128 plus 1)that in hexadecimal format is 41
REMEMBER TO INSERT COUNTRY TABLE
E.G.Data creazione 31/10/99 15.38 7 / 7 f19intro

THE SECOND METHOD to enter service mode is to use the LOCAL KEY BOARD
as describe here below
1. Starting from TV off press VOLUME + on the LOCAL KEYBOARD and in the
mean time switch on the TV with the mains switch
2. Within three second switch on the TV using the "SWITCH-OFF" button on the
Remote Control
3. A small windows with black background and yellow characters will appear in the
middle of the screen.
PARAMETER VALUE
4. Using the Remote control, program + / - (top bottom) will change the
"PARAMETER" and the VOLUME + / - (left / right) will change the value
5. Each parameter can be stored, leaving the service mode, by using the MEM
(yellow) button on the remote control
6. To leave "SERVICE MODE" without to store the new value use the TV button.
7. It is not necessary to store each value one by one this means that you can
change all value you need and finally leave the SERVICE MODE pressing the
YELLOW button MEM.
In the Table 3 we can find all parameter and related value to be seated. Some
parameter have to adjusted with a simple on-off value, others are just factory option and
more others must be adjusted with value that are expressed in hexadecimal form ranging
from 0 to FF (that is from 0 to 63 in decimal form ).
Table 3 represent the value to be assigned to three parameter to properly set options:
Table 3 Option bye (1, 2 and 3) value and related meaning
BIT OPTIONB1 OPTIONB2 OPTIONB3
WEIGHT 0 1 0 1 0 1
0 BG 2° SCART FSU
1 L/L' MUST BE 1 BACKGROUND
2 I CINCH HOTEL
3 DK SVHS NTSC M
4 X RGB UV1316
5 X X V. GUARD
6 E.E.TXT W.E.TXT X
7 CATV X
E.G.Data creazione 31/10/99 15.38 4 / 7 f19intro

PICTURE IN PICTURE
MODULE

SDA 9288X
PICTURE IN PICTURE
1 General Description
The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of
a video signal (inset channel) for the purpose of combining it with another video signal
(parent channel). The easy implementation of the IC in an existing system needs only a
few additional external components. There is a great variety of application facilities
professional and consumer products (TV sets, supervising monitors, multi-media, …)
Data Sheet
• 212 luminance and 53 chrominance pixels per inset line for picture size 1/9
• 6-bit amplitude resolution for each incoming signal component
• Field and frame mode display
• Horizontal and vertical filtering
• Special antialias filtering for the luminance signal
16:9 compatibility
• Operation in 4:3 and 16:9 sets
• 4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively
Analog inputs
• Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)
Analog outputs
• Y, + (B-Y), + (R-Y) or Y, – (B-Y), – (R-Y) or RGB
• 3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)
Free programmable position of inset picture
• Steps of 1 pixel and 1 line
• All PIP and POP positions are possible
2 picture sizes
• 1/9 or 1/16 of normal size
High resolution display
13.5 MHz/27 MHz display clock frequency
Freeze picture
I 2 C Bus control
SDA 9288X P.I.P. Pagina 1 di 4 e.g. sda9288xR.doc

Threefold PIP/POP facility
• Three different I 2 C-addresses (pin-programmable)
System Description
AD Conversion, Inset Synchronization
The inset video signal is fed to the SDA 9288X A141 as analog luminance and
chrominance components 1) . The polarity of the chrominance signals is programmable.
After clamping the video components are AD-converted with an amplitude resolution of 6
bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375
MHz clock for the chrominance signals.
For the adaption to different application the clamp timing for the analog inputs can be
chosen (CLPS; CLPFIX). Setting this bits to ‘1’ can be useful for non-standard input
signals.
For inset synchronization it is possible to feed either a special 3-level signal via pin HVI
(detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal
and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset
channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL
compatible levels by a simple external circuit. Centering of the displayed picture area is
possible by a programmable delay for the horizontal synchronization signal (HSIDEL).
The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock
and the AD converter clocks are derived from the parent horizontal synchronization pulse
or from the quartz frequency converted by a factor of 4/3.
Delay differences between luminance and chrominance signals at the input of the IC
caused by chroma decoding are compensated by a programmable luminance delay line
(YDEL) of about – 290 ns … 740 ns (at decimation input
By analyzing the synchronization pulses the line standard of the inset signal source is
detected and interference noise on the vertical sync signal is removed. For applications
with fixed line standard (only 625 lines or 525 lines) the automatic detection can be
switched off.
The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a
correct detection of the field number is possible, an important condition for frame mode
display.
Input Signal Processing
SDA 9288X P.I.P. Pagina 2 di 4 e.g. sda9288xR.doc

This stage performs the decimation of the inset signal by horizontal and vertical filtering
and sub-sampling. A special antialias filter improves the frequency response of the
luminance channel. It is optimized for the use of the horizontal decimation factor 3:1.
A window signal, derived from the sync pulses and the detected line standard, defines the
part of the active video area used for decimation. For HSIDEL = ‘0’ the decimation window
is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse.
For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines
standard decimation starts in the 26th video line.
The realized chrominance filtering allows omitting the color decoder delay line for PAL and
SECAM demodulation if the color decoder supplies the same output voltages independent
of the kind of operation. In case of SECAM signals an amplification of the chrominance
signals by a factor of 2 is necessary because just every second line a signal is present.
This chrominance amplification is programmable via pin SYS or I 2 C Bus (AMSEC). The
horizontal and vertical decimation factors are free programmable (DECHOR, DECVER).
Using different decimations horizontal and vertical 16:9 applications become realizable:
DECHOR = ‘1’, DECVER = ‘0’: picture size 1/9 for 4:3 inset signals on 16:9 displays
DECHOR = ‘0’, DECVER = ‘1’: picture size 1/16 for 16:9 inset signals on 4:3 displays
PIP Field Memory
The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812
bits. The picture size depends on the horizontal and vertical decimation factors.
In field mode display just every second inset field is written into the memory, in frame
mode display the memory is continuously written. Data are written with the lower inset
clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz).
Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems.
For progressive scan conversion systems and HDTV displays a line doubling mode is
available (LINEDBL). Every line of the inset picture is read twice. Memory writing can be
stopped by program (FREEZE), a freeze picture display results (one field).
Having no scan conversion and the same line numbers in inset and parent channel (625
lines or 525 lines both) frame mode display is possible. The result is a higher vertical and
time resolution because of displaying every incoming field. For this purpose the standards
are internally analysed and activating of frame mode display is blocked automatically when
the described restrictions are not fulfilled.
As in the inset channel a field number detection is carried out for the parent channel.
SDA 9288X P.I.P. Pagina 3 di 4 e.g. sda9288xR.doc

Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed by omitting or inserting lines when the read
address counter outruns the write address counter.
The display position of the inset picture is free programmable (POSHOR, POSVER).
The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz)
after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this
position the picture can be moved over the whole display area. Even POP-positions
(Picture Outside Picture) at 16:9 applications are possible.
Horizontal Decimation PIP PIXELS per Line
Having different line standards in inset and parent channels we have a so called mixed
mode display. It causes deformations in the aspect ratio of the inset picture. A special
mixed mode display is available for the picture size 1/9 (MIXDIS):
Synchronization of memory reading with the parent channel is achieved by processing
the parent horizontal and vertical synchronization signals in the same way as described
for the inset channel. The synchronization signals are fed to the IC at pin HP/SCP for
horizontal synchronization and pin VP for vertical synchronization. In the same way as
described for the inset channel the burst gate of the sandcastle signal can be used for
horizontal synchronization. In scan conversion systems also the inputs HPD/SCI and
VPD/VI are available if the input HVI is activated for inset synchronization.
2.4 Output Signal Processing
At the memory output the chrominance components are demultiplexed and linearly
interpolated to the luminance sample rate. Different output formats are available:
luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB.
For the RGB conversion 3 matrices are integrated: Matrix selection is done by pin SYS or I
2 C Bus. The matrices are designed for the following input voltages (100 % white, 75 %
color saturation):
SDA 9288X P.I.P. Pagina 4 di 4 e.g. sda9288xR.doc

TDA8310A
PAL/NTSC colour processor
for PIP applications
FEATURES
• Video switch with 2 CVBS inputs. One input can beswitched between CVBS and Y/C and the circuit can
automatically detect whether the incoming signal is CVBS or Y/C
• Integrated chrominance trap and bandpass filters (automatically calibrated)
• Integrated luminance delay line
• Automatic PAL/NTSC decoder which can decode all standards available in the world
• Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications
• Horizontal PLL with an alignment-free horizontal oscillator
• Vertical count-down circuit
• RGB/YUV and fast blanking switch with 3-state output and active clamping
• Low dissipation (560 mW)
• Small amount of peripheral components compared with competition Ics
GENERAL DESCRIPTION
The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications.
The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted
in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal
and vertical synchronization and an RGB/YUV switch.
The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the
circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP
processor are:
• Luminance signal
• Colour difference signals (U and V)
• Horizontal and vertical synchronization pulses.
• The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the
SCART input signal.
• The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package.
FUNCTIONAL DESCRIPTION
CVBS switch
The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C.
The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals.
It is also possible to force the switch to CVBS or Y/C.
TDA8310A CHROMA DECODER FOR PIP Pagina 1 di 2 e.g. TDA8310A.doc

Synchronization circuit
The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed
level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude.
The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first
PLL has a very high static steepness this ensures that the phase of the picture is independent of the line
frequency.
The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of
internal components an automatic adjustment circuit has been added to the IC.
The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in
a free-running frequency which deviates less than 2% from the typical value.
The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the
output pulse is 5.4 ms, the front edge of this pulse coincides with the front edge of the sync pulse at the input.
The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 ms. Both the
horizontal and vertical output pulses will always be available at the outputs even when no input signal is
available. In addition to the horizontal and vertical sync pulse outputs
the IC has a sandcastle pulse output which contains burst key and blanking pulses.
Integrated video filters
The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are
automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C
signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit
however, it is also possible to force the filters in the CVBS or Y/C position.
The luminance delay line is also realised by gyrator circuits.
Colour decoder
The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference
demodulators. The 90° phase shift for the reference signal is achieved internally.
The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard
decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the
IC.
The decoder can be forced to one of the standards via the ‘forced mode’ pins. The crystal pins which are not used
must be connected to the positive supply line via a 8.2 κΩ resistor. It is also possible to connect the non-used pins
with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 κΩ divided by the
number of pins.
The chrominance output signal of the video switch is externally available and must be used as an input signal
for the SECAM decoder.
RGB/YUV switch
The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be
set to high-impedance state so that other switches can be used in parallel.
The switch is controlled via pins 13 and 52.
TDA8310A CHROMA DECODER FOR PIP Pagina 2 di 2 e.g. TDA8310A.doc

th
INTB
PH1LF
V P1
HOUT
VOUT
SAND
V P2
30
37
COINCIDENCE/
NOISE
DETECTOR
22, 29
i.c.
33, 34
n.c.
DEC FT
15
CHROMINANCE
BANDPASS
32
CVBS SW
PHASE
DETECTOR
SYNC
SEPARATOR
DEC BG
35 21
CHROMINANCE
TRAP
DEC DIG
19 41
VCO
+
CONTROL
VERTICAL
SYNC
SEPARATOR
FILTER
TUNING
REF
PULSE
SHAPER
39
HORIZONTAL/
VERTICAL
DIVIDER
36
TDA8310A
40
SANDCASTLE
GENERATOR
RGB/YUV
SWITCH
10
11
12
13
14
8
7
6
5
1
2
3
52
4
28
R1
G1
B1
BLANK1
CLAMP
R
G
B
BLANK
R2
G2
B2
BLANK2
IDENT
HUE
AUTOMATIC
Y/C
DETECTOR
INPUT
SELECTOR
PAL/NTSC
DECODER
LUMINANCE
DELAY LINE
49
Y
31
20
17
9
16
47
48
46 45
PLL
XTAL4
44
XTAL3
43
XTAL2
42
XTAL1
27 26
25
24
23
50 51
18 38
MGD128
CVBS EXT CHROMA I SECAM
GND2 CVBS INT SYST SW CHROMA O
R/W COLOUR2 LOGIC2
COLOUR1 LOGIC1 B Y
R Y
GND1
GND3

PINNING
SYMBOL PIN DESCRIPTION
R2 1 RED input 2 (PIP)
G2 2 GREEN input 2 (PIP)
B2 3 BLUE input 2 (PIP)
IDENT 4 colour standard identification output
BLANK 5 blanking output
B 6 BLUE output
G 7 GREEN output
R 8 RED output
SYST SW 9 CVBS/system switch
R1 10 RED input 1
G1 11 GREEN input 1
B1 12 BLUE input 1
BLANK1 13 blanking input 1
CLAMP 14 clamping pulse input
DEC FT 15 decoupling filter tuning
CHROMA I 16 chrominance input
CVBS EXT 17 external CVBS/Y input
GND1 18 ground 1 (0 V)
V P1 19 supply voltage 1 (+8 V)
CVBS INT 20 internal CVBS input
DEC DIG 21 decoupling digital supply rail
i.c. 22 internally connected (test purposes)
LOGIC2 23 crystal logic 2 input/output
LOGIC1 24 crystal logic 1 input/output
COLOUR2 25 colour system logic 2 input/output
COLOUR1 26 colour system logic 1 input/output
R/W 27 read/write selection input
SYMBOL PIN DESCRIPTION
HUE 28 HUE control input
i.c. 29 internally connected (test purposes)
INTB 30 internal bias
GND2 31 ground 2 (0 V)
CVBS SW 32 CVBS positive/negative modulation
control switch input
n.c. 33 not connected
n.c. 34 not connected
DEC BG 35 bandgap decoupling
VOUT 36 vertical sync output pulse
PH1LF 37 phase 1 loop filter
GND3 38 ground 3 (0 V)
HOUT 39 horizontal sync output pulse
SAND 40 sandcastle pulse output
V P2 41 supply voltage 2 (+8 V)
XTAL1 42 4.4336 MHz crystal
XTAL2 43 3.5820 MHz crystal for PAL-N
XTAL3 44 3.5756 MHz crystal for PAL-M
XTAL4 45 3.5795 MHz crystal for NTSC
PLL 46 PLL colour filter
CHROMA O 47 chrominance output for TDA8395
SECAM 48 SECAM reference output
Y 49 Y output
B−Y 50 B−Y output
R−Y 51 R−Y output
BLANK2 52 blanking/insertion input 2 (PIP)

TDA8395
SECAM DECODER
FEATURES
• Fully integrated filters
• Alignment free
• For use with baseband delay
GENERAL DESCRIPTION
The TDA8395 is a self-calibrating, fully integrated SECAM decoder. The IC should
preferably be used in conjunction with the PAL/NTSC decoder TDA8362 or TDA8366 and
with the switched capacitor baseband delay circuit TDA4660. The IC incorporates HF and
LF filters, a demodulator and an identification circuit (luminance is not processed in this
IC). The IC needs no adjustments and very few external components are required. A
highly stable reference frequency is required for calibration and a two-level sandcastle
pulse for blanking and burst gating.
FUNCTIONAL DESCRIPTION
The TDA8395 is a self-calibrating SECAM decoder designed for use with a baseband
delay circuit.
During frame retrace a 4.433619 MHz reference frequencyis used to calibrate the filters
and the demodulator. Thereference frequency should be very stable during this period.
The Cloche filter is a gyrator-capacitor type filter theresonance frequency of which is
controlled during the calibration period and offset during scan; this ensures thecorrect
frequency during calibration.
The demodulator is a Phase-Locked Loop (PLL) type demodulator which uses the
frequency reference and the bandgap reference to force the PLL to the required
demodulation characteristic.
The low frequency de-emphasis is matched to the PLL and is controlled by the tuning
voltage of the PLL.
Secam secoder TDA8395 Pagina 1 di 2 e.g.TDA8395R

Fig.1 Block diagram.
PINNING
Fig.2 Pin configuration
SYMBOL PIN DESCRIPTION
f ref/ IDENT 1 reference frequency
input/identification input
TEST 2 test output
V P 3 positive supply voltage
n.c. 4 not connected
n.c. 5 not connected
GND 6 ground
CLOCHE ref 7 Cloche reference filter
PLL ref 8 PLL reference
−(R−Y) 9 −(R−Y) output
−(B−Y) 10 −(B−Y) output
n.c. 11 not connected
n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
SAND 15 sandcastle pulse input
CVBS 16 video (chrominance) input

A digital identification circuit scans the incoming signal for SECAM (only line-identification
is implemented). The identification circuit needs to communicate with theTDA8362 to
guarantee that the output signal from the decoder is only available when no PAL signal
has been identified. If a SECAM signal is decoded a request for colour-on is transmitted to
pin 1 (current is sunk). If the signal request is granted (i.e. pin 1 is HIGH therefore no
PAL) the colour difference outputs (-(Β-Y) and -(Ρ-Y)) from the TDA8362 are high
impedance and the output signals from the TDA8395 are switched ON. If no SECAM
signal is decoded during a two-frame period the demodulator will be initialized before
another attempt is made also during a two-frame period. The CD outputs will be blanked or
high-impedance depending on the logic level at pin 1.
A two-level sandcastle pulse generates the required blanking periods and, also, clocks the
digital identification pulse on the falling edge of the burst gate pulse. To enable The
calibration period to be defined the vertical retrace is discriminated from the horizontal
retrace, this is achieved by measuring the width of the blanking period.
Secam secoder TDA8395 Pagina 2 di 2 e.g.TDA8395R

TEA6415C
BUS-CONTROLLED VIDEO MATRIX SWITCH
DESCRIPTION
• 20MHz BANDWIDTH
• CASCADABLE WITH ANOTHER TEA6415C (INTERNAL ADDRESS CAN BE
CHANGED BY PIN 7VOLTAGE)
• INPUTS (CVBS, RGB, MAC, CHROMA, ...)
• POSSIBILITY OF MAC OR CHROMA SIGNAL
• FOR EACH INPUT BY SWITCHING-OFF THE
• CLAMP WITH AN EXTERNAL RESISTOR BRIDGE
• BUS CONTROLLED
• 6.5dB GAIN BETWEEN ANY INPUT AND OUT-PUT
• -55dB CROSSTALK AT 5MHz
• FULLY ESD PROTECTED
GENERALDESCRIPTION
The mainfunctionof the IC is to switch 8 video input sources on 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the
lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB
signals).
Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal
the align-ment is switched off by forcing, with an external resistor bridge, 5 VDC on the
input. Each input can be used as a normal input or as a MAC or Chroma input (with
external resistor bridge). All the switch-ing possibilities are changed through the BUS.
Driving 75Ω load needs an external transistor. It is possible to have the same input
connected to several outputs.
The starting configuration upon power on (power supply : 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1
word of 16 bits is necessary to determine one configura-tion
TEA6415C video matrix switch Pagina 1 di 1 e.g. TEA6415C.doc

TDA4665
Baseband delay line
FEATURES
• Two comb filters, using the switched-capacitor technique, for one line delay time (64 ms)
• Adjustment-free application
• No crosstalk between SECAM colour carriers (diaphoty)
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals (±(Ρ-Y) and ±(Β-Y))
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle
pulse (64 ms line)
• Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour
GENERAL DESCRIPTION
The TDA4665 is an integrated baseband delay line circuit with one line delay. It is suitable
for decoders with colour-difference signal outputs ±(Ρ-Y) and ±(Β-Y).
TDA4665 Crhroma Delay line Pagina 1 di 3 e.g.TDA4665.doc

handbook, full pagewidth
±(R−Y)
colour-difference
input signals
16
SIGNAL
CLAMPING
pre-amplifiers
LINE
MEMORY
SAMPLE-
AND-HOLD
LP
addition
stages
output
buffers
11
±(R−Y)
colour-difference
output signals
±(B−Y)
V P1
sandcastle
pulse input
14
9
5
SIGNAL
CLAMPING
analog supply
SANDCASTLE
DETECTOR
FREQUENCY
PHASE
DETECTOR
LINE
MEMORY
DIVIDER
BY 192
SAMPLE-
AND-HOLD
3 MHz shifting clock
LP
TDA4665
12
2
6
13
15
±(B−Y)
n.c.
n.c.
n.c.
n.c.
LP
6 MHz
CCO
DIVIDER
BY 2
7
i.c.
10
digital supply
1
3
4, 8
GND1
V P2
GND2
MED848

SAA55xx
Standard TV microcontrollers with On-Screen Display (OSD)
1 FEATURES
• Single-chip microcontroller with integrated On-Screen Display (OSD)
• Versions available with integrated data capture
• One Time Programmable (OTP) memory for both program Read Only Memory (ROM)
and character sets
• Single power supply: 3.0 to 3.6 V
• 5 V tolerant digital inputs and I/O
• 29 I/O lines via individual addressable controls
• Programmable I/O for push-pull, open-drain and quasi-bidirectional
• Two port lines with 8 mA sink (at

S
1.531.01S
R5
390
C1
470N
100
+6V
R4
4,7
C8
10
R1
100
R2
100
C2
100N
C3
100N
C4
L1
100µH
C6
470N
R3
10K
C7
1µ
16V
QZ1
24,576MHZ
1 PCLK
2 NICAM data
3 I2C addr1
4 SCL
5 SDA
6 VSSA1
7 VDEC1
8 IREF
9 Port 1
10 SIF2
11 VREF1
12 SIF1
13 I2C addr 2
14 VSSD1
15 VDDD1
16 RESET CAP
17 VSSD4
18 XTAL IN
VDDD264
Line outR 63
Line outL 62
Main outL 61
Main outR 60
VDDA3 59
AUX outL 58
AUX outR 57
VSSA3 56
PCAPL 55
PCAPR54
VREF3 53
Sc2 outL 52
Sc2 outR 51
VSSA4 50
VSSD2 49
Sc1 outL 48
Sc1 outR 47
C11
470N
C21
47µ
16V
L2
100µH
C19
10N
C20
10N
R6
820
C18
470µ
10V
+6V
L3
100µH
C12
2µ2
16V
R7
12
C22
2µ2
16V
C23
2µ2
16V
A3-A
A3-B
A3-C
1
C13
2µ2
16V
+6V
2
R25
10K
3
C15
2µ2
16V
C14
2µ2
16V
C25
2µ2
16V
R19
10K
R8
10K
C24
2µ2
16V
R26
47K
R27
47K
R9
10K
C16
2µ2
16V
C17
2µ2
16V
R20
47K
R21
47K
R12
47K
+6V
R10
47K
R28
1K
+6V
R13
47K
TR4
BC848
R29
1K
R11
47K
R22
1K
TR1
BC848
R14
1K
TR3
BC848
C27
2µ2
16V
C28
2µ2
16V
TR2
BC848
R15
1K
R30
1K
+26V
R16
470
R17
1K2
R18
1K2
R23
1K2
R24
1K2
C26
470µ
35V
Industrie Formenti Italia s.p.a.
Stabilimento di Sessa Aurunca (CE)
Stereo-Nicam i.c. per Telaio F19
06/07/1999 531.01S
531.00S
Di Maio
Cod. Schema:
Sost.schema:
Descr.
Data:
Scala:
Disegnato: Approvato:
C9
10
19 XTAL OUT
20 PORT2
VREF2 46
I.C. 45
C31
47µ
16V
C29
2N2
C30
2N2
R31
10K
R32
10K
21 SYSCLK
22 SCK
23 WS
I.C. 44
VSSA2 43
I.C. 42
C38
100µ
16V
R33
1K8
C39
100µ
16V
R34
1K8
24 SDO2
25 SDO1
I.C. 41
VREF(N) 40
5 6 7 8
IC3 TDA2822M
4 3 2 1
IC2
KIA7812
7
5
C5
1000µ
10V
6
+6V
8
12
11
10
9
C10
470N
26 SOI2
VREF(P) 39
27 SDI1
VDEC2 38
28 TEST1
Sc2 InL 37
29 MONO IN Sc2 InR 36
30 TEST2
VSSD3 35
31 Ex InR
Sc1 InL 34
32 Ex InL
Sc1 InR 33
IC1 TDA 9870A
R35
270
C32 C33
470N 47µ
16V
C34
330N
R36
15K
R37
15K
C35
330N
2
C36
2µ2
16V
1 4
C37
2µ2
16V
3
3 2 1
C42
C40
1000µ
1000µ
16V
16V
C41
1000µ
16V
R38
R39
4,7
4,7
C43 C44
100N 100N
+26V
10 4 7 3 6
+26V
C45
2µ2
16V
R40
2K2
5 8
9
C46
2µ2
16V
R41
2K2
1
2
A1-G
A1-E
A1-F
A1-H
A1-L
A1-K
A1-J
A1-I
A1-B
A1-A
A1-D
A1-C
A2-J
A2-D
A2-G
A2-C
A2-F
A2-E
A2-H
A2-I
A2-A
A2-B
SC1/
SC2
CINCH
OUT
SC
CUFFIA
AP
BB

531.01S

Industrie Formenti Italia s.p.a.
Stabilimento di Sessa Aurunca (CE)
Disegnato: Approvato:
Descr.
Sost.schema:
Cod. Schema:
Data:
Scala:
+26V
+12V
+6V
+26V
+26V
+12V
+12V
+6V
+6V
+12V
+6V
+12V
+8V
+6V
+8V
+12V
+6V
C58
2µ2
16V
R5
2K7
R18
1K
R31
2K7
R16
120
R62
10K
C20
2µ2
16V
C59
2µ2
16V
C62
1000µ
16V
C63
1000µ
16V
C67
100µ
16V
R59
15K
C30
100
R60
15K
C57
2µ2
16V
C66
100µ
16V
C43
10N
C50
47µ
16V
C51
470N
R58
270
C52
330N
C53
330N
R61
10K
C47
47µ
16V
R38
47K
C11
100N
R64
1K
C39
2µ2
16V
L8
6.8µH
R10
22
C41
2µ2
16V
C68
1000µ
16V
1
2
3
4
5 6 7 8
IC4
TDA2822M
R22
47K
C42
2µ2
16V
C23
100N
C33
100N
C65
2N2
C19
100N
1
2
3
IC5
KIA7812
R39
47K
TR7
BC848
C64
2N2
R63
1K
R9
47K
C35
100N
R46
47K
R35
47K
R50
1K
TR12
BC848
R49
47K
TR11
BC848
R47
1K
R54
1K2
R55
1K2
C56
2µ2
16V
R41
47K
R40
47K
R20
22K
R53
1K2
R70
4,7
R69
4,7
R57
10K
R56
10K
C49
2µ2
16V
C48
2µ2
16V
R23
47K
C55
2µ2
16V
C45
47µ
16V
L1
77,8
MHZ
C54
2µ2
16V
C34
10
7
A1-G
C14
1N
R4
22K
C3
2µ2
16V
R71
1K
R28
47K
C4
2µ2
16V
C18
100N
TR6
BC848
R19
1K
C6
10N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IC1
TDA 9811
TR8
BC848
C21
100N
R25
12K
R21
1K
C25
100N
R27
47K
R26
10K
C24
100N
C22
100N
C73
10n
1 3 2
IC2
L78M08CS
C26
1µ
16V
R24
100
C1
1µ
16V
C2
100N
R3
22K
9
A1-I
C44
10N
5
A1-E
12
A1-L
8
A1-H
C60
2µ2
16V
C61
2µ2
16V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
IC3 TDA 9875
C36
10
QZ1
24,576MHZ
C8
1N
C28
100N
C29
100N
10
A1-J
5
A2-E
8
A2-H
9
A2-I
2
A1-B
1
A1-A
4
A1-D
3
A1-C
6
A2-F
7
A2-G
3
A2-C
1
A2-A
2
A2-B
4
A2-D
10
A2-J
11
A1-K
R45
47K
R48
47K
R52
1K2
R51
470
R43
1K
TR10
BC848
R42
1K
TR9
BC848
L3
100µH
R65
10K
R66
10K
R68
1K8
R67
1K8
C46
470µ
35V
C32
1µ
16V
C31
470N
R34
390
C12
1000µ
16V
TR5
BF 959
R17
3K9
R13
150
R12
1K
TR4
BF 959
R15
120
R14
47
C13
1N
L2
1µH
R11
100
FOS1
K9453
R7
4K7
C10
100N
R8
47K
TR3
BC848
C9
100N
TR2
BC848
R6
4K7
C7
1N
C15
470µ
10V
L4
100µH
R44
12
R72
2K2
R73
2K2
C37
470N
1
A3-A
2
A3-B
3
A3-C
C38
2µ2
16V
C70
2µ2
16V
C71
2µ2
16V
R36
270
C17
470N
C5
1000µ
10V
C69
470µ
16V
6
A1-F
R37
820
R2
22K
L7
100µH
R74
18
R1
220
R77
1K2
C72
220µ
16V
R78
100
R75
270
F1
TPS
6,5
TR1
BC848
R76
1K5
L5
100µH
R33
4,7
R32
10K
C27
470N
R79
10K
R29
100
R30
100
D1
LL103
BA682
BA782
BA783
D2
LL103
BA682
BA782
BA783
FOS2
K3953M
C40
1000µ
10V
BB
2
5
4
2
1
3
3
5
4
1
VIF1
VIF2
Cbl
VIF3
VIF4
AP
TAdj
Tpll
CsAgc
STD
CVBS
LSW
NC
NC
NC
NC
NC
SIF2
SIF1
INSW
Vp
CvAgc
GND
CUFFIA
SC1/
SC2
CINCH
VREF1
SIF2
Port 1
IREF
SIF1
VSSA1
I2C addr1
NICAM data
PCLK
SCL
SDA
I2C addr 2
VSSD1
VDDD1
RESET CAP
Cref
05/07/2000
VoAf
MUTE
TAGC
VoQss
Sc2 outR
Vo
Vi
Sc2 outL
AFC
VCO1
XTAL IN
VCO2
S
PORT2
SYSCLK
SCK
WS
SDO1
SDO2
SDI1
SOI2
TEST1
MONO IN
TEST2
Ex InR
Ex InL
Sc1 InR
Sc1 InL
Sc2 InR
Sc2 InL
I.C.
I.C.
I.C.
I.C.
VSSA2
VREF2
Sc1 outR
Sc1 outL
VREF(N)
VREF(P)
VDEC2
VSSD3
VSSD2
VSSA4
XTAL OUT
VSSD4
VDEC1
PCAPL
VDDD2
Line outR
Line outL
Main outL
Main outR
VDDA3
AUX outL
AUX outR
VSSA3
PCAPR
VREF3
OUT
SC
511.04S
511.05S
Di Maio
1.511.05S
Stereo-Nicam per Telaio F19

C62
IC5
C50
J3
C49
IC4
C67
FOS1
C66
L8
C68
C38
C72
C53
C52
J10
C51
J6
C48
C54
C63
J9
C40
IC1
A1
A2
R28
C47
L1
FOS2
IC3
L7
J8
F1
C32
C15
IC2
QZ1
J4
TR5
C17
TR4
L2
C45
C55
R20
C4
C3
R33
C71
L4
L3
C58
C59
C60
C61
R59
R60
J2
R30
R29
R37
R44
C46
L5
C12
C5
J5
C39
C70
J7
C20
C1
R74
C69
A3
C56
C42
C57
C41
C26
1.511.05S
1 12
1 10
TOP SILK

BOT.ELEC.
1.511.05S

I
+
+
1 2
3
4
5
6
7
8
9
10
11
12
SOLO PER SINTESI DI TENSIONE
SOLO PER SINTESI DI FREQUENZA
SOLO PER MONO
SOLO PER MONO BG
SOLO PER MONO BG/L L"
SOLO PER STEREO
SOLO PER DOPPIA SCART
SOLO CON SINGOLA SCART
H
G
F
E
D
C
B
A
J115
+5V
R102
J113
D100
15K
+5V
1N4148
R137
R138
15K 15K
+12V
21
Status
COPY
AV1 9
R141 5K6
R183
7 SC1toSC2
STEREO NICAM
10K
C259
R142
R103
SWITCH
AV
15K
R140 5K6
10µ
C112 10K
6 SC1/SC2
A8
8
16V
100n
R258 560
PWM
RIGHT IN
D101
+5V
+12V +12V
2
10µ
1N4148
Status
C261 16V
LEFT IN
AV2
+5V
10
8 5 6 10
4 3 2 1
10 7
9
12 5 11
R133R132
J116
7 9
8 6 3 4
1 2
6
C249
12K 12K
R273
R244 J25
R257 560
47K
VIDEO IN
R143
ADC
J30
10µ
R139
+12V
20
10K
15K
16V
J145
J38
150
J8
SWITCH
TR110
JS13
+12VC113
8
+12V
J53
J29 J33
TR211
5
R168
BC848
CINCH/SC
BC848
100n +5V
9
47K
C279
R271
C274 C275
R248
13
C496 9 8 7 6 5 4 3 2 1 C484
100n
C280
R185
2µ2
+8V5
R272
IC201
150
1n 1n
100
17
10K
PORT 3
2µ2
560
C246
100n
100V
J31 +12V +12V +12V +12V
+12V
J22
JS7
LA7955
+12V
18
R177
100V
10µ
15K
R169
L401
C289
IC203
C245
14
100n
16V
J118
+5V
J91
J89
100K
47MH
L7806CV
4 8
R291
C290
R314 R274
10µ
C248
IC400
12
1
1 A15-A
A400-A
47
560 12K
R179 3° SYS
330n J62
16V
10
TDA1521A
R297
R298
R299 R300
1
5 10µ
LEFT
R277
TR111
R424 R425
2
1
3
2
A400-B
2 A15-B
C454
TDA2613
4K7
2K7 2K7
16V 47K
12
BC 548B
47K
R166
C495 82 82
J75
C247
3
9
1n
100 L207
F204
R287
TR212
15K
1n
10µ
R184
SWITCH
R290 1µH
L9454M
100
BC848
C401
C404 C405 D205
16V
R278
100K
3
1n 1n
1
1 4
7
R233
L/L"
J142
J138
2K7
J146
VIDEO OUT
220µ
12K
19
Status
C283 C282
30
25V
100µ 100n
TR213
16 15 14 13 12 11 10 9
19
20
R167
L481
47
PIP
PORT 2
BF 959
BA 682
R288
JS450
47µH
16V
IC102 TDA 9830
+5V
J101
8
R296 C285 D206
150
C256
7
2 5
18
16
R256
LEFT OUT
15K
JS105
R491 82
1 2 3 4 5 6 7 8
10µ
C400 J102
J139
3
Status
C255
1K
4
J114 R174 J52
C451
16V
+5V
2
C281
3
17
R279
560
CTI
100n
1n BA 682
10µ C272
Status
2200µ
1n
R293
R310
330
R146
JS490
3
H1
TR214
11
+12V
4
BF 959
12
11 16V 1n
Cuffia
15K
R450 35V
J24
JS104
TR218
+5V
J87 +27,8V
8,2
J140
4
150
15K
0
47K
BC848
5
13
15
R255
RIGHT OUT
R490 82
R294
R306
C288
1
JS102
Status
R312
1K5
JS525 JS526
R286
+5V
R128
330n
5
J90
JS451 L480
47
J72
J9
14
C273
560
0
Formato
R402
2K7
TR217
120
C254
+5V
47µH
BC 548B
1n
8,2
10µ
C450
+5V
J100
C295
C257
2 10 6
15K
C402
L400
JS201
J2
16V
BLUE
JS100 22n
2200µ
100n
C286 C287
C291
10µ
TR103
32
0
47MH
4µ7 4µ7
C278
35V
4 A400-D
10µ
16V
SC2
BC848
100N
R131
RIGHT
R289 R292 R295 C284
16V 16V
16V
JS202
+12V
C413
3
J4
A400-C
15K
1K 120
120 1n
R308
DSC
22n
C250
R150
2
C482 C481 C483
4K7
R307
1000µ
270
X13
2200µ 2200µ 68n
+12V R304
R285
C406 C407
1K
16V
R157
+5V
35V 35V
1n 1n
1K
R311
47K
120
R235 C251
R190
TR219
1K5 100N C299
C298
BC848
+5V
+27,8V
+12V J21
330
8K2
TR215
R531
10µ
10µ
C506
R313
BC 548B
4K7
16V
16V
R172
J45
2K7 100
TR500
C575
100K
R302
TR216
JS9
220µ
BC 548B
BC 550C
R575
TR102
GREEN 33
Voltage
25V
C296
47K
4K7
BC848
1 Tuning
100n
JS8
R509
R507
R530
R576
C292
R186
220K
4K7
5K6
4K7
10µ
270
29
J95
+12V
J6
CORB
D
1,5Vpp
R305
16V
R158
J13
+12V
R508
1K
R189 1K
C265
+5V
1K2
J47
IC200
S
R525
330
100µ
P
R303
47
R262
+5V +12V
15
R301
16V
J15
HEF4053
AUDIO out
VOL.
L
TR575
0,5Vpp 18K
47K
47K
TR101
RED 34
A
BC848
J17 10
C240
BC848
Y
R165 R161
R526
10µ
15K
AFC
330
10K
PLL
15
2
C577
16V
R577
SWITCH
SW.
1
J27
R187
1µ
ADD SCL SDA
+33V AGC +5V +5V IF2 IF1
4K7
+
EXT.S.in
CH3
R159
15
2
J19 JS203
270
TR525
R162
SW TV/AV
TR107
VOLUME
AUDIO
1K
R200
BC848
+12V
BC848
PLL IF 5
IC200-B
C263
AFC
RIGHT IN
R188
47K R160
1n
S.T.
11
J23
390
R264
C239
330
100K
C214
UHF VHIGH VLOW
TUN
AGC
+5V IF2 IF1
4
47K R263
10µ
+5V
100n
55 De Emph.
R528
+5V
14
12
R527
47K
16V
TR501
L201
1K 100
3
13
TEXT
BC858
BV53
SOUND MUTE
C264
CH2
INTERFACE
3 4 5
-106
3n3
R265
D103
R163
2 9 1 6 7
AUDIO
35
8
10 11
SOUND
IC200-A
J32
BLNK
47K
C293
1µH
1 5 IF 49
PRE AMP
LEFT IN
R503
X7
56
9
S.DEC
1n
+MUTE
5
1N4148
0
4K7
VIDEO IF
R173
14
J108
R505
C501
+5V
4
J28
UHF
F203
1K
R502
AMPLIFIER
C233
C237
330n
C551
JS501
K3953 2
IF 48
R240
3
33K
C550
4
+ PLL DEMOD.
10µ
100
TR209
PAGE
2K2
C503
470µ
R192
20 VHF-H
100n
16V
BC 548B
J35
J111
J107
680
RAM
+5V
100n
10V
3
J49
100K
IC200-C
TR503
R510
JS500
PLL FM
F575
C500
14
+12V 16
390
GND
TELETEXT
BC858
DEMOD.
R239
H 2,5Vpp
100n R501
21
J86
12K
+5V
J44
IC200-D
ACQUISITION
VHF-L
J144
ADJ.
J122
+8V
C111
R512
C277 R269
100n
CVBS0 23
560
4K7
R241
100n 47K
J5
J40
+8V
6 7 8
R208
C244
R513
R267 R223
10K
100n
DATA
F576
330
C110
2K7
C576
C216
J63
R242
100n
24
C504
54
1
J10
CVBS1
SLICER ACQUISITION
JS502
R224
SIF
47n
TIMING
R123 R121 R122
2K2
12K
Tuner AGC
LIMITER
R209 390 R227
TR203
100n
D104
AGC FOR
680
BC 548B
15K 15K 15K
+5V TR502
C231
680
C232
68
CH1
R119
C502
R261
C242
+5VSTBY
53 IF + TUNER
L206
1K
R114
BC858
47µ
1µ
F201
VIDEO IN
330N
100n
+5V
26
X5
J41
IF AGC
R578
J109
R268
820
Iref
18K
3,3µH 4,5-6,5
R506 16V 1N4148
16V
VIDEO
390
75
PORT 0
VIDEO
C236
R229
24K
R511
10K
C230
AMPLIFIER
+8V
25
J3
TR210 100
1K
C109
S.FILTER
4K7
C505
2µ2
TOP
MUTE
J20
BC848
H 2Vpp
R504
100n
9
J110
100n
16V
Bandgap
D102
POL
R212
1
+12V
C206
F200
21
1N4148
R309
75
R118
KEY1-A 2K2
2µ2
5,5
J148
36
18
J126
VIDEO
R145
H.Sync
KEY2
2
C203
ANA-
MUTE
16V
C235
R231
4K7
100N
R551 R552
10µ
75
22K
100
3
L205
100 100
GND
H 2,5Vpp 16V
+8V
C238
KEY1-B
6,8µH
R144
4 SEL
44
1000µ
18
22K
CONTROL DAC
R201
FRAME
27
17
6 VIDEO out
R228
16V
DISPLAY
KEY1 J125 R117
5
C267 D203
1x8 BITs
TR201 J42
H 2,5Vpp
AV
+5V
8
TIMING
10µ ZTK
14x6 BITs
1K
TR200
TR204
KEY1-C
BC858
1K
100
6 ANA+
100V 33B
1x4 BITs
R259
BC848
BC848
R230 47
VIDEO OUT
D108 H 5,6Vpp
R116
2K7
16
19
KEY0 J124
7
12 Supply
TR202
1N4148
R206
C294 10µ
37
+8V
J39
R107
V.Sync
KEY1-D
BC848
R252 560
R202 100
1K
R232
16V
RIGHT OUT
100
8 P-
SCL 7
J43 C213
1
1K
1K
I2C BUS
IDENT
C207
10µ
9
1000µ
R205 C201
R214
C258
R254 560
J133
R203 100
TRANSCEIVER
100n
H 1Vpp
16V
RIGHT IN
KEY1-E
SDA 8
10V
330
18
75
10
2
R210
Xout
P+
42
13 CVBS int
10µ
1K
C297
R251 560
J14
16V
LEFT OUT
3
Xin
R213
41
J16
VIDEO CVBS
38 CVBS1 out
C208
10µ
150
C260
J7
R253 560
V 5Vpp
OSCILLATOR
R115
IDENT SWITCH
C300
47n
16V
LEFT IN
19 ON/OFF
6
QZ100
SAT
82
12MHZ
40
17
J61
Xgnd
CVBS input
1K
H 1,4Vpp
+3V3
H 1Vpp H 1,4Vpp
VIDEO IN
J120
20
R171 R170 +5V
C204 100n
R105
C103 C102 J121
I2C
5K6 5K6
Yin 27
11 SVHS-Y
J18
4
18 18
1
J123
+5VSTBY
CD MATRIX
5
R154
+8V
B-Y in
J127VDDP
44
J99
31
SAT CONTROL
9
15K
JS4
BLUE STRETCH
C268 C269
R249 C270 C271
50
13
D105 R176
C101
MSDA R100 100
J141
ZPD
DATA
SKIN TINT CORR
SVHS-C
C212 2n2
470n
32
14
10K
43
10
J34
1n
1n
100 1n 1n
80C51
R-Y in
2V4
RESET
MICRO-
17
ADDRESS
R178
D106
CONTROLLER
49 MSCL R101 100
TR220
Yout 28
C209 22n
R282 220
23 Rin
R
RED IN
1N4148
BC848
LUMA DELAY
D107
100
15
R153
R191 10K
1N4148
52
J76
PEAKING
SW 16/9
TR108
JS2
R-Y out 30
CORING
24 Gin
C210 22n G
R283 220
GREEN IN
4K7
BC 548B
+12V
R260
BLACK STRETCH
11
330
JS3
B-Y out
SW
+5V
29
RGB MATRIX
VSSP
+5V +12V
25 Bin
C211 22n
R284 220
38
B
J60
BLUE IN
ROM
RGB1 INPUT
7
16K TO 128K
J97
1
R156
CVBS -Y/C
D201
R106
FBlank
39
R164
10K
J64
26
FB
VDDC
SWITCH
BLNK
+3V3
2
J77
16
1
15K
R147
BAT 81
45
J98
3
C243 C262
SW AM/FM
BASE BAND REF
+8V5
470 470
47K
4
12 11 10 9 8 7 6 5 4 3 2 1
DELAY LINE
PIP
J78
CHROMA TRAP
C104 C105
SRAM
TR105
+12V
+
100µ 100n
256 Bytes
47 INTO J117J136
IR IRR100
BC 548B
5
+12V
R245 R246 R247 R250
SC1
BANDPASS
10V
100 100 100 75
R104
Vcc
6
A10
TO RGB
R155
C253
100K +12V
J50
1000µ
1
R113
4K7
31
GND
CTI - 16:9
1
VDDA
PORT 1
R219
16V
+3V3
+5VSTBY
12 11 4 3 5 2 8 7 6 9 10 1
VCC
1
+5VSTBY
+8V
37
BLACK-
BL.Curr. R281 10K
DRAM
J135
C221 3N3
FILTER
18
C106
R181
A7
2 2
4,7
CURRENT
C150
3K TO 28K
LED1
R236 R226 R225
TUNING
100µ
10K
36
A11
REF
STABILISER
D200
100n
J149 R151
J54
470K 470K 470K C220
Colour PLL
3
10V
QZ202
C276
ZPD
3
+5V
R182
100n R207
100
470
3,58205
D109
J137
C223 C222
33
19
PIP
COL.AUT.
12K
Chroma Ref
Blue
R215
8V2
4
R148
TR206
51
4
SW.XTAL 1N4148
100n 100µ BFS 19
100K
10V R238
SecPllDec 16
100
5 5
47K
TR208
C215
PAL/NTSC
RGB CONTROL Green
R216
TR109
20
SCL1 R126 5K6
BC 548B 47K
220n
46
BC 548B
R237
XTAL 4,43
SECAM
+
+5VSTBY
+5VSTBY
6 6
TS
R180
IC600 STV 5112
VSSC
QZ201 C205 18 -3,58
DECODER
OUTPUT
100
13
100K
A5
35
C218 J36
4,43
WHITE P.
R217
R39
R127 5K6
47K
1K
48
21 Red
SDA1
22n
TR8
5
J65
A9
C219 18
R40
BC
28
C100
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VPE
R211
XTAL 3,57
SYNC SEP.
100
4
15
1
560
547B
68n
JS200
+
H 100Vpp
+5VSTBY
1st LOOP
TR7
+3V3
VSSA 22
3
47K
QZ200
22 Beam Current
C217 TR205
C602 22
BC
J119
J51
3,57954
HUE
CONTR. BRIG.
2
22n BFS 19
547B
MHZ
RED 6 6
R613
8 1
R152
1 ONLY FOR
VCO +
H 2Vpp
TIMER/
Vsawtooth 51
H 2Vpp
H 2Vpp
A601-F R601 680
IC100
AUTOMATIC
C252
CONTROL
C234 J46
H 70Vpp
68K
D5
C107
Ctrs
0
100n
2n2
ZPD
7 2
2
100µ
52
2V7
SAA5553M3
TESTING
V Iref
C603 82
10V
V 3Vpp
H 100Vpp
R175
V 1,8Vpp
R270
VERTICAL H/V
R243
D202
6 3
GREEN 5
R614
39K 2% VdriveA
+5VSTBY
47 GEOMETRY DIVIDER
5
A601-E R602 680
15K
4K7
C266 BA 157
68K
5 4
VdriveB 46
2µ2
100V
C604 27
IC101
R220
230V
2 1
ST24C04CB
VERT. SYNC
43 Phi-1 15K
BLUE 4
R615
R276 J37
50
4
3
EHT
SEPARATOR
J73
A601-D R603 680
H 100Vpp
+8V
68K
C229 C228
100K
R275
R43
D21 R36
3
GND 3
1n 1n
33K
~
A601-C
AvlCap
10K
C80
47K
R37
BA 157
R34
R604 R605 R606
D602
R280
EW-drive 45
10µ
12K
CUT
1K 1K 1K
EW-
47K
1N4148 R628 100
+8V
100V
OFF 2
R600
GEOMETRY
C227 C226
JS12
MOUNTED
2
10K
R221
100
4n7 1µ
A601-B
D28 R38
1K
D600
D601
JS1 OR JS6
16V
R59
C615
C225 Phi-2 42
+12V 1 1
1N4148
1N4148
C6 C7
100
J84 2n2
39 Digi DEC
2n2 150µ R30 R31
T1
D9
39K
BA 157 47K
A601-A
C614
3
2nd LOOP
C81
D611
400V 400V 330K 330K
JS1
BYV95C
C60 68
D607 R629
D605
2n2
C50
680n
A4
BAV103
2
15 2 +148V
+
ZPD 82
1N4148
1KV
+148V/128V
HOR. OUT
C12
47n
200V 1 1
9V1
A1
JS6
C19 C20
Sand. 41
R612
1
R2 33n
D610
C613
4 +128V
IC204
100n 100µ
R54
C224
C601 C600
1K
68K 630V
BAV103
220
250V 250V
+28V STBY
40
1
H. out
100n
100n 47µ
R616
C18
TDA 8844
2 2
16V
D609
330
J93
+8V
11
27K
R611
B
A6
BAV103
C612
1K8
D10
500V
+27,8V
R88
1K
D604
H 500Vpp D7
R16 BYV95C
J79
R87 6V3 3 3
220
2
0
TASTO1
TR4
1N4148 R617
BYV95C L4
TIP 115
R65
H 27Vpp
R610
3
6
H 8Vpp
0,1
0,39
C611
1K8
G
0,1
R19 R20
1K
1K
D603
1 2 3
C25
J88
110
220
R3
C24
4K7 4K7
1N4148
R618 3
H 10Vpp
2200µ
FUS1 X2
4K7
100n
8
TR1
35V
IC202
R
T2AH
C2
C14
C21
R25
1K8
C3
STH7N90FI
2K2 L78M08CS
EAT
D606
250V
4n7
470
10
330
11
4n7
1N4148
500V
R33 R4
2000V
500V
500V
IC10 TDA 8138
1 2 3 +8V
10 9 5 7 1
R620 120K
R621
4,7 47
TR3
H 120Vpp
R1
D6
R5
R17
BC848
J48
+8V
L2 L3
D1 D2
11 8
1 2 3 4 5 6 7 8 9
J82
12
10M
J74
C53 68n
J147
J83
R93
R91 R90
R622
R619
47MH
1N4007 1N4007
100
TR600
150K
1N4148
4,7
3
560
R626
L5
0,1
1K8
C10
R6
C241
4K7
150K 150K
R81
BF 422
X12
C8
C78
L22
C9 L1
220n
47
1000µ
R92
1K2
C610
47µ D13
R7
D11
R23
D20
+8V
+28V STBY
BV52-105
680N 47MH
R24
X8 10V
J71
150n 22K
2n2
BV53-117
25V BA157
BYV95C
10K
D53
BV52-109
G2
400V
D3
D4
2K2
100V
R623
C607
1KV
2*47MH
1N4148
C606
R624
C608
10K
560
C605
2µ2
EAT
1N4007 1N4007
+12V
R51
1N4148
R75
C79
D27
2µ2
100n
12
C28
J12
C62
+8V
T2
R83
FOC
100n
250V
C26
TR11
56 R76 R77 R94
L21
TR16 R82 15K
100n
BA 157 L23
250V
1M
250V
1000µ
6n8
D50
R79
250V
C4
C5
5 6 7 8
J55
100n
J134
BC858
820 820 820
BU 508D 15K
400V
C609
R18
16V
J96
33K
1N4148
D608
R627
4n7
4n7
IC1 TDA 4605
C30
1
9
R625
10µ
X1
C15
0,1 C22 330
1,5
100µH
18K
1N4004
470K
DEGAUSS
500V
500V
1000µ
R50
5,6 µH
C74
100V
4 3 2 1
A12 J105
C32
4n7
500V
R71 D204
C65
C73
25V
1
3
BV53-130
10µ
2
100 H1Vpp
16
J106
2K2 1N4148
470µ
D26
1µ J68
10
BA 157
250V
C23 330
3K3
35V
D23 R80
250V
J26
D8
C72
C77
1 2 3 A600-C
X10
500V
2
R66
J1
1
R8
C51
1µ
150n
A2
1
3 2 1
R32 1N4148 9
6
10K
V 5Vpp
2200µ
+12V
47
J59
1
R84
BA 157
350V
G2
C1
100K
16V
25V
L24
39
390K
3
J66
J70
FOC
A3
BV53
10n
PTC1
R9
R12 R13
R15 4M7
J131
C54
C66
4
J104
7
1 2 3
-120
250V
JS10 X3
J132 X4
22n
4n7
D12
+5VSTBY
4
8
TR207
R64
BC 338-40 H 40Vpp
2
560K
820 3K9 R14
BYW95A
0,1
R89
C59
R56
H 12Vpp
2K2
C27
100µ C82
D24 H 1200Vpp
C75
0,1
J92
1,8
C17
R26
1000µ
5
J85
25V 100µ
R60
BY228
J94
C29
R29
V 11Vpp
C68
+148V/128V 5n6
LIVE AREA
6
2n2
4K7
10V
25V
TR15
1000µ
220
10n
C70
400V
R10 C11 R11
C16
400V
BC 639
C71
16V
R28
4K7 TR6
6
C67
V 12Vpp
2n2 1µ
R85 10
4K7 4n7 220
1µ
2µ2
1,5KV
COMPONENTI SOTTO RETE
BC 638
C56
1,6KV 100V
R86
63V
R73
100V
R67
R70 L20
J103
2
A3
10n
47K
5W
0,1
220
7
C76
JS11
R266 R61
TR5
R68
R57
D22 R78
L26
+5V
1 3
680n
H 8Vpp 220 10K
82K
0,1 10MH
BC 548B
C31
390
4,7
BA 157 10K
1,2mH
250V
Non inserire con modulo zero power
R27
8
J67
5
C55 C52
1000µ J112
1K
220n 470µ
10V J128 X14X6
A3
J69 J57
C69
D25
R35
Solo con modulo zero power
50V
9
3 1
T3 12K
22n
BA 157
D52
C61
R21
R53 3
400V
L25
BA
100n
TR2
IC5
TR12
610µH * *
157
270
R69
250V
BC 548B
TDA 8351
82K BUK474
J56
Industrie Formenti Italia s.p.a.
R22 47K
C58
R58
VERT.
200A
J130
* MOUNTED L25
47K
22
22n
H 60Vpp
YOKE
OR L26
R55 H 150Vpp
Stabilimento di Sessa Aurunca (CE)
V 1Vpp
0,1
V 45Vpp
C57
Descr. TELAIO BASE F19
220n
+8V5
A3
R42 75
D51
Data: 12/09/2000 Cod. Schema:
4
497.07B
Scala:
Sost.schema: 497.06B
R41 75
BA 157
1
2
A14-B
A14-A
3
+26V
A13-G
L. AP OUT
A13-I
4
A13-H
R. AP OUT
A13-E
EX.L. OUT
A13-F
EX.R. OUT
A13-J
GND
A13-D
GND
-
-
5
A13-C
+12V
SDA
A13-B
A13-A
SCL
SW TV/AV
IF1
6
7
AM/FM IN
8
+6V
L.SC OUT
R.SC OUT
INTER.
GND
+12V
LSCin
RSCin
9 10
A600-A
A600-B
11
Disegnato:
DI MAIO
Approvato:
12
H
G
F
E
D
C
B
A

D602
D107
R8
C291
D28
R617
L480
C246
R527
J30
R625
R32
C4
C15
R21
C216
J24
C245
D605
R603
R618
C299
J83
JS11
C401
C52
L22
R100
C267
C76
D7
C208
D601
R87
D20
D11
D10
J72
C614
R13
L400
R15
C107
C451
C247
L481
D604
C402
X2
R513
C406
C404
C222
R230
A6
DIS1
C101
R200
R606
J36
R9
D106
R7
R623
C32
C256
J42
L1
L2
L206
L21
R5
C265
D202
D1
R151
C8
C19
L4
C2
R311
R268
D24
K1
C14
A5
D204
C9
R85
D51
IRR100
IC600
TR108
L24
R219
C11
K3
R224
R90
R605
D3
C71
C206
C5
L207
C232
R153
K2
A15
C255
R613
R11
R33
C607
L3
C261
R244
C250
R104
R602
C254
R116
IC200
F576
D4
R117
R118
F575
C260
C1
R4
A2
A11
R233
C259
A10
C240
IC204
C18
C20
J147
C604
R3
TR8
R159
TR16
C238
D9
TR7
D2
K4
SC2
SC1
J110
A7
R25
A601
R601
T1
TR4
C57
X1
PTC1
A1
R94
R142
R76
C58
K5
D201
F200
F201
R18
QZ202
C226
QZ201
F203
D101
D100
C606
C253
QZ200
X13
IC100
QZ100
C239
C28
R626
R614
C605
D600
C252
C481
C577
F204
A8
IC102
C230
L201
C213
J50
TR214
TR213
C283
C248
R122
R144
C298
IC201
R102
C55
D13
IC101
C106
C31
R167
IC202
A13
C233
C286
TR217
TR216
R501
TR215
C292
R114
R50
TR111
TR6
TR5
TR500
C241
TR208
R89
R101
TR109
C501
D104
C231
C287
R26
A12
C3
C56
R58
C12
C104
R106
R505
C551
R504
C407
A400
C405
L401
R121
T3
TR12
IC5
IC10
IC203
IC400
TUNER
KEY1
R123
CH2
CH3
CH1
LED1
C258
TR1
R105
C297
C257
C294
IC1
R10
D103
D105
H1
JS12
TR2
C249
C74
A4
L26
C51
D52
L25
C75
R64
D27
R88
D21
R84
R20
R19
D12
C23
C29
R57
R56
R70
C54
R91
R82
C72
C73
C79
R83
D26
C68
L20
R86
R55
D25
C70
C69
R79
D23
R80
A3
L5
D6
R1
FUS1
R2
R31
R30
C7
R6
C16
D8
R12
C78
R77
R17
C22
C21
C30
R92
C61
C65
TR15
T2
D22
R75
C25
C24
R81
J41
TR203
C484
C496
J43
J44
JS10
J19
J92
C482
J18
J37
J122
JS7
J128
J130
J25
J35
J93
J70
J140
J139
J138
J5
J102
J133
J17
J94
J16
R152
J26
J14
J81
J65
J1
J3
J71
J22
J109
D203
J132
J134
J48
J116
J53
J101
J144
J60
J100
J6
J20
J8
J68
J10
J117
J39
J28
J56
J12
J63
J120
R24
J115
J113
J55
J32
J27
J46
J112
J38
J45
J54
J4
J124
J125
J2
J106
J74
J31
J23
J136
J118
J135
J137
J119
J75
J126
J79
J82
J64
J57
J90
J141
J143
J21
J62
J34
J7
J9
J52
JS1
R188
R189
R190
TASTO1
R14
C10
R156
J87
TR105
J77
R276
J108
J86
J107
C575
J145
J84
J85
J88
J76
R309
J105
R181
J96
J98
J97
J89
J91
C502
R147
J104
J103
D108
R53
R16
TR207
R71
J66
R266
C67
C66
L23
C27
C59
J67
TR209
C235
R201
J40
L205
J61
C266
J95
JS502
J51
D200
A9
R240
J78
J47
J49
J69
J73
R145
J59
J148
C50
J146
X3
X5
X14
X6
A14
D50
D53
C80
C81
C77
R425
R424
R490
R491
JS490
JS450
JS451
J149
D109
C293
X8
C263
JP2
JP1
JP4
JP3
JP5
R619
TR600
C608
R620
CRT
A600
R624
R622
C609
C610
D608
R621
D606
C601
R604
D607
R615
C602
C603
D603
R628
X10
R627
X12
R616
C600
R600
R629
C17
C6
JS13
R113
D102
R243
J127
D5
J131
X4
J121
C82
LA7955
LIVE AREA
F19
T2AH
00 01 02 03 04 05
MICROCONTROLLER
SDA
GND
11Vpp
GND
R
L
GND
GND
+12V
GND
GND
GND
GND
230Vac
GND
2,5Vpp
45Vpp
1200Vpp
GIALLO
SCL
GND
+8V5
+12V
GND
VIDEO
IN
SEL
BIANCO
+5V
GND
ANA+
GND
+128V
GND
+5V STBY
LEFT
IN
GND
P+ P-
GND
G F M A M G L A S O N D
ANA-
GND
GND
+8V5
+12V
GND
GND
+12V
+12V
GND
+12V
+12V
+148V
+5V
+5V
GND
GND
DSC
+5V
+5V
+5V STBY
+8V5
497.07B
GND
GND
GND
DEGAUSS
GND
GND
GND
GND
RGB
GND
G2
NVM
+12V
GND
AGC
JS6
GND
GND
5,6Vpp
+5V STBY
SCL
SDA
3
1
1
3
1
2
3
4
1Vpp
60Vpp
27Vpp
150Vpp
2,5Vpp
+5V
12Vpp
120Vpp
1Vpp
40Vpp
8Vpp
497.06B
RIGHT
IN
ROSSO
1,8Vpp
3Vpp
1Vpp
10Vpp
500Vpp
5Vpp
2,5Vpp
2,5Vpp
HEF4053
0,5Vpp
12Vpp
+5V
STBY
+5V
+12V

497.07B