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Pulse and Digital Circuits Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
iv. During the period T < t < 3T/2, that is, between 2 to 3 ms, the output decays.
1.0
10
At t = 3 ms v
o
=
f
At 3 ms, the input falls by 100 V. Hence
V g
= V – 100 = 19.73 V
f
V = V e
e = 132.32 (0.9048) = 119.73 V.
v. During 3T /2 < t < 2T, that is, d uring 3 to 4 ms, the output decays.
1.0
10
0.1
At t = 2T= 4 ms, v
o
= V
h
= V g
e = 19.73 e =17.85 V.
V
j
= V
h
+ 100 V = 17.85+100=117.85 V.
In a few cycles, the output reaches the steady state.
Steady-state response:
Under steady state, the output is symmetrical with respect to zero volts, since the
capacitor blocks dc. Therefore, the dc component in the output is zero.
Let V 1 be the voltage at t = 0
t
For 0 < t < T/2, v
o
= V1
e
'
0.1
At t = T/2=1 ms, vo
= V1
= V
1e
= 0.905 V
1
'
V
1
= 0.905 V
1
(3)
As the input abruptly falls, output also falls by the same amount to V 2 .
(tT / 2)
For T/2 < t < T v
o
= V
2
e
'
0.1
At t = T, v o
= V 2 = V 2
e = 0.905 V 2
'
V2 = 0.905 V
2
(4)
For symmetrical wave
' '
V
1
= V 2
and V
1
= V2
(5)
'
'
V
1
V2
= 100 V and V1
V 2
= 100 V (6)
'
From (6), we have V1 V2
= 100 V (7)
And from (3), we have V1
= V2
(8)
'
Substituting (8) in (7), we have V
1
+ V 1
= 100 V (9)
'
From (3), we have V
1
= 0.905 V
1
Substituting in (9)
0.905V 1
+ V
1= 100 V
1.905V 1
= 100 V.
'
V
1
=52.49 V and V 1
= 0.905V 1
= (0.905)(52.49)= 47.50 V
' '
From (5) as V
1
= V2
an d V1
= V2
'
V 2
= –52.49 V V 2
= –47.50 V
We can now plot the steady-state response as we know
'
V = 52.49 V
V = 47.50 V
1 1
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