vulcan-cryptanalysis

Pin 2 is cryptovariable input. It conveys the cryptovariable from the key
loader to the IC during key loading operations. It is connected directly to the
CV shift register seen at the far right of the chip.
Pin 3 is plaintext input. It connects to some switching logic near the top center
of the die. The switching logic routes plaintext and ciphertext to the appropriate
circuits depending on whether the chip is operating in encrypt (transmit)
or decrypt (receive) mode.
Pin 4 is TX/RX input. It selects whether the chip encrypts (TX) or decrypts
(RX). This signal connects to the same switching logic circuitry as Pin 3.
Pin 5 is ciphertext input. It connects to a differential decoder and then to
the switching circuitry that routes it appropriately based on whether the chip
is encrypting or decrypting.
The un-bonded pin between Pin 5 and Pin 6 is a test output that is inaccessible
external to the chip. This test pin allows the contents of the 128-bit SRAM
(discussed later) to be read, presumably to enable testing of the SRAM during
manufacturing. We have deliberately chosen not to give this pin a number since
it has no function during normal operation.
Pin 6 is V+, the positive supply voltage. It supplies Vdd to all the transistors
on the chip.
Pin 7 is ciphertext output. It is differentially encoded and is valid only
during encrypt (transmit) operations.
Pin 8 is clock input. It allows an externally sourced clock signal to act as a
time base for all synchronous logic on the chip. External inputs to the chip are
clocked in on the rising edge of this clock. The nominal clock rate should be 12
KHz during encrypt and decrypt operations, but we observe that the DVP key
loader supplies a faster clock than this during key loading.
Pin 9 is WE (write enable) input. When active (low), it allows the CV shift
register to operate, clocking in CV bits from Pin 2 in accordance with the clock
signal on Pin 8. Circuitry on the chip creates a single clock cycle delay between
the WE input and the clock and CV inputs, an observation that is important
when analyzing the exact temporal relationship of these three signals.
Pin 10 is output-enable input. This signal must be high in order for ciphertext
out (Pin 7) and plaintext out (Pin 11) to produce outputs. If Pin 10 is low,
ciphertext out and plaintext out will be in high impedance states.
Pin 11 is plaintext output. It connects to the bottom of the XOR tree and
is only valid during decrypt operations.
Pint 12 is ground. It provides Vss to all the transistors on the chip.
2.2.2 Circuitry
The large repetitive structure directly in the center of the chip is a static random
access memory (SRAM) array of 128 bits, arranged as eight rows by sixteen
columns. Address decoding circuitry is present immediately to the left of and
immediately below the SRAM array. The SRAM address is determined by bits
held in the shift register along the left side of the SRAM array.
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