vulcan-cryptanalysis

ciphertext comes from the output of the XOR tree during encrypt (TX) and
comes from the differential decoder during decrypt (RX).
The rightmost of these switching circuits selects the input of the XOR tree.
The XOR tree input comes from plaintext in (Pin 3) during encrypt (TX) and
comes from the output of the differential decoder during decrypt (RX).
The XOR tree, visible as a vertical column of circuitry in between the modified
ciphertext shift register and the CV shift register, has 10 stages, each of
which accepts an input from the previous stage, conditionally modifies this input,
and then provides an output to the next stage.
The modification performed by each stage of the XOR tree is simply a conditional
exclusive-or (addition modulo-2), conditioned on the value of the corresponding
bit of CV from the CV shift register. The two bits being added
modulo-2 are the input to this stage of the XOR tree and a corresponding bit
of modified ciphertext from the modified ciphertext shift register.
Certain stages of the XOR tree behave differently from the aforementioned
general rule. Specifically, the first stage of the XOR tree is further modified by
the value of C1/C2 (Pin 1). The last stage of the XOR tree never performs an
XOR (i.e. acts as though the corresponding CV bit is always 0). The secondto-last
stage of the XOR tree always performs an XOR (i.e. acts as though the
corresponding CV bit is always 1). All other stages perform the XOR only if
the corresponding CV bit is 1. If the corresponding CV bit is 0, the output of
this stage is the same as its input.
Immediately below the modified ciphertext shift register is a circuit that
delays the WE signal by one clock cycle and then combines this signal with
the master clock to create a clock signal for the CV shift register. The overall
effect is that the CV shift register only clocks when WE is 0, and the effect of
transitions on WE is delayed by one clock cycle relative to all other signals.
The circuitry between Pin 7 and Pin 8 is a pair of test transistors. The
thin column of circuitry at the far right edge of the SRAM array is pre-charge
circuitry for the SRAM. All I/O input pins have diode protection and series resistance
to guard against damage. This concludes our description of the SC76807
circuitry. We turn now to the overall operation of the device.
2.3 Modes of Operation
The SC76807 IC can operate in at least three different modes: encrypt, decrypt,
and key loading. Each of these modes affects how input and output signals are
processed by the IC. Although the SC76807 IC is the device that performs the
cipher operations, the overall DVP module itself consists of additional circuitry
that we have not described here because it is not particularly interesting or
relevant.
During encrypt, the DVP module delivers plaintext CVSD bits to Pin 3
of the SC76807 and receives ciphertext bits from Pin 9 of the SC76807. The
TX/RX input on Pin 4 must be low. Each bit-wise encrypt operation requires
the clock signal on Pin 8 to transition from low to high once the plaintext input
is stable. The ciphertext output bit is retrieved on the falling edge of the clock
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