implementation of turbo decoder using max-log-map ... - ijater

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The MAP algorithm provides the best performance in BER while its complexity is higher than the two-step SO- VA. II. Turbo Encoder Structure International Journal of Advanced Technology & Engineering Research (IJATER) (A) B. ML-MAP SISO Decoder Architecture Fig. 2 Turbo encoder structure A generic structure for turbo encoding based on parallel concatenation of two Recursive Systematic Convolutional (RSC) encoders is given in Fig 2. Two identical RSC encoders produce the redundant data as parity bits. The input data stream and parity bits are combined in series to form the turbo coded word. The size of the input data word may vary from 40 bits to 6144 bits for UMTS [1] and take specified values such as 378, 570, and 20730 for CDMA2000 [6] turbo coding which are the two main standards of 3GPP and 3GPP2 respectively. III. Turbo Decoder A. Turbo Decoder Structure Figure 4 shows the SISO decoder architecture which consists of the forward and backward state metric, LLR computation, and memory (LIFO and FIFO) blocks. The FIFO 1 and 2 are used to Buffer the input data symbols and the LIFO 3 and 4 are to store the forward state metric and the LLR values, respectively. The SISO decoder has been built with two backward state metric units, β1 and β2. α and γ denote the forward state and branch metric units. Fig. 4 SISO Architecture The ML-MAP algorithm can be used for reduced complexity decoder implementation [4].The decoding process in MAP algorithm performs calculations of the forward and backward state metric values to obtain the log likelihood ratio (LLR) values, which have the decoded bit information and reliability values. The LLR values are represented by the Following equation [6]: Fig. 3 Iterative Turbo- Decoder The turbo decoder structure represents two soft-input soft-output (SISO) decoders and one interleaver/deinterleaver between them. Decoding process in a turbo decoder is performed iteratively through the two SISO decoders via the interleaver and the deinterleaver. As shown in Figure 3. When the Maximum A Posteriori (MAP) algorithm is applied to each SISO decoder, the Log-Likelihood Ratio (LLR) for each double-binary pair can be expressed as equation (A) [7]: k-1. The equation of γ, α, and β can be represented to logarithm form as shown below [3],[6]: ISSN No: 2250-3536 Volume 2, Issue 4, July 2012 247
International Journal of Advanced Technology & Engineering Research (IJATER) The main kernel of the Turbo-Viterbi algorithm is ADD-COMPARE-SELECT (ACS) operation which is performed by Forward recursion, Reverse recursion and dummy reverse recursion blocks. There are 8 parallel ACS blocks and hence 8 states can be processed in parallel. Fully parallel architectures assign one ACS for each state to meet the performance constraints on speed and latency [5]. Where the branch metric (γ) is calculated by the a priori information (Le), channel reliability value (Lc), input Symbols (x and y1), the systematic bit (uk s) and the parity bit (uk p). As described in previous section, a priori information is obtained from the LLR value computed in previous decoding process after subtracting the input symbol data and a priori values from the LLR value. The MAP algorithm, which uses the above equations, is not suitable for hardware implementation due to the logarithm function. This problem can be addressed using a well know approximation, called Jacobi logarithm, which is given below. 1. Branch And State Metric Unit: The branch and state metric units (BMU and SMU) are implemented using ML-MAP algorithm. The conventional BMU and SMU consists of branch metric calculation, add, compare, select, and normalization processes which is shown in fig 5. The general SMU in turbo SISO decoder must include the normalization process to avoid overflow of the state metric values [3]. This approximation is used to implement the state metric unit (SMU) and LLR computation unit (LCU) in Log MAP and ML-MAP SISO decoder. The 2nd term of the right hand side in equation (4) is a correction term which can be implemented through a simple look-up table [3]. However, the correction term is ignored in this paper as we have implemented ML-MAP SISO decoder. C. Specifications Complexity studies showed that Max-Log-MAP is the Best compromise between performance and complexity when compared with MAP, Log-MAP and SOVA. Therefore, our implementation will be based on the Max-Log- MAP algorithm. Regarding Turbo decoder implementations, several interesting implementations were recently proposed, most of which are based on fixed-point arithmetic [6]. Since fixed-point operations require multiplications and divisions for normalization, computational complexity is still high. In this paper, we propose an integer based Turbo decoder. The turbo decoder considered in this paper has the following specifications: I. Code rate R = 1/3. II. Puncturing pattern: even/odd parity. III. Block size: N = 40 to 6144 bits. IV. Interleaver: S-random interleaver with S = 8. Fig. 5 conventional structures of the branch and state metric units The branch metric values are obtained from input data symbols. The new state metric values are calculated in single clock cycle recursively using add, compare (C), select, and normalization (N) processes from branch metric and state metric values [3],[6]. The critical path delay is determined by the above processes. In the proposed architecture which is shown in fig 6 the normalization is done in the branch metric values itself. This normalization method leads to a simplified SMU (shown in fig.7) [3], but more complex in BMU. The novel architecture reduces the critical path delay significantly by eliminating the state metric normalization process used in the conventional SMU [6]. D. Implementation ISSN No: 2250-3536 Volume 2, Issue 4, July 2012 248
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