TDA7200 - Infineon

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TDA7200 Applications T A has to be calculated as T A = R1⋅ ( R R1 + R F 3int F 3int + R + R F 4int F 4int ) ⋅C13 = R1II( R F 3int + R F 4int ) ⋅C13 ... for ASK and T A = R1 + R R1⋅ R F 3int F 4int + R F 4int ⋅C13 = R1II ( R F 3int v + R F 4int ) ⋅C13 ... for FSK R1, R F3 int , R F4 int and C13 see also Figure 7 and Figure 9 19 20 U threshold 25 data filter CM data slicer Figure 7 Data Slicer Threshold Generation with External R-C Integrator In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with an internal resistive divider and one capacitor as shown in Figure 8. For selecting the peak detector as reference for the slicing level a logic low as to be applied on the SSEL pin. In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is selected (see Figure 9). In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so the peak detector can not be selected. The capacitor value is depending on the coding scheme and the protocol used. Data Sheet 24 V 1.0, 2007-05-02
TDA7200 Applications C Pins: 26 25 peak detector 56k 390k U threshold data slicer CP Figure 8 Data Slicer Threshold Generation Utilising the Peak Detector 3.6 ASK/FSK-Data Path Functional Description The TDA7200 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback connection between the threshold voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK switch amplifier. In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-reference level. The slicing reference level is generated by an internal voltage divider (R T1int , R T2int ), which is applied on the peak detector output. The selection between these modes is controlled by Pin 16 (SSEL), as described in Section 3.5. This is shown in Figure 9. Data Sheet 25 V 1.0, 2007-05-02
Page 1 and 2: Data Sheet, V 1.0, May 2007 TDA7200
Page 3 and 4: Data Sheet, V 1.0, May 2007 TDA7200
Page 5 and 6: TDA7200 Table of Contents Page 1 Pr
Page 7 and 8: TDA7200 Functional Description 2 Fu
Page 9 and 10: TDA7200 Pin No. Functional Descript
Page 15 and 16: TDA7200 Functional Description 2.3
Page 17 and 18: TDA7200 2.4.6 FSK Demodulator Funct
Page 19 and 20: TDA7200 Applications 3 Applications
Page 21 and 22: TDA7200 Applications 3.2 Data Filte
Page 23: TDA7200 Applications injection of t
Page 27 and 28: TDA7200 Applications asymmetrical o
Page 29 and 30: TDA7200 Applications In order to re
Page 31 and 32: TDA7200 Applications Uc Us Figure 1
Page 33 and 34: TDA7200 Reference Table 7 Operating
Page 35 and 36: TDA7200 Reference # Parameter Symbo
Page 43 and 44: TDA7200 Reference 4.3 Test Board La
Page 45 and 46: TDA7200 Reference Ref. Value Specif
Page 47 and 48: TDA7200 List of Tables Page Table 1
Page 49: www.infineon.com Published by Infin

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