RAiO RA8806 - Display Future

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Version 1.3 RA8806 Two Layers Character/Graphic LCD Controller (Continued) REG# Name D7 D6 D5 D4 D3 D2 D1 D0 Default C0h TPCR1 TP_EN TP_SMP2 TP_SMP1 TP_SMP0 TPWAK _EN ACLK2 ACLK1 ACLK0 00h C1h TPXR TPX9 TPX8 TPX7 TPX6 TPX5 TPX4 TPX3 TPX2 00h C2h TPYR TPY9 TPY8 TPY7 TPY6 TPY5 TPY4 TPY3 TPY2 00h C3h TPZR -- -- -- -- TPY1 TPY0 TPX1 TPX0 00h C4h TPCR2 MTP_MD -- -- -- -- -- MTP_PH1 MTP_PH2 00h D0h PCR PWM_EN PWM_DIS_ LEV -- -- PCLK_R3 PCLK_R2 PCLK_R1 PCLK_R0 00h D1h PDCR PDUTY7 PDUTY6 PDUTY5 PDUTY4 PDUTY3 PDUTY2 PDUTY1 PDUTY0 00h E0h PNTR PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0 00h F0h FNCR ISO8859_E N -- -- -- MCLR ASC ASC_SEL1 ASC_SEL0 00h F1h FVHT FH1 FH0 FV1 FV0 -- -- -- -- 00h RAiO TECHNOLOGY INC. 12/193 www.raio.com.tw
Version 1.3 RA8806 Two Layers Character/Graphic LCD Controller 5-2 Register Description STATUS Register (RS = 1, ZWR = 1) Bit Description Access 7 Memory Write Busy Flag 0 : Not busy. 1 : Busy, when font write or memory clear cycle is running, the busy R flag = 1. 6 SCAN_BUSY 0 : Not busy. 1 : When driver scan logic is not idle(i.e. XCK is active), SCAN_BUSY R = 1. 5 SLEEP 0 : Normal mode. R 1 : Sleep mode. 4-3 NA R 2 Wakeup Status bit (The same with REG[0Fh] Bit-2.) R 1 0 KS Status bit (The same with REG[0Fh] Bit-1.) TP Status bit (The same with REG[0Fh] Bit-0.) R R REG [00h] Whole Chip LCD Controller Register (WLCR) Bit Description Default Access 7 Power Mode 0 : Normal Mode. All of the functions of RA8806 are available in this mode. 1 : Sleep Mode. When RA8806 is in Sleep mode, all of functions enter 0 R/W off mode, except the wake-up trigger block. If wake-up event occurred, RA8806 would wake-up and return to Normal mode. 6 Linear Decode mode This bit is used to define the Font ROM address mapping rule. The standard product is set to 0. And 1 for special application that when user a want to create a new Mask Code. 0 R/W 0 : BIG5/GB ROM mapping rule. 1 : User-defined ROM mapping rule. 5 Software Reset 0 : Normal Operation. 1 : Reset all registers except the contents of Display Data RAM (Only 0 R/W work at Normal mode). When this bit set to “1”, the next MPU cycle for RA8806 have to wait 3 clocks at least. 4 Reserved 0 R 3 Text Mode Selection 0 : Graphical Mode. The written data will be treated as a bit-map pattern. 1 : Text Mode. The written data will be treated as an ASCII, BIG5 or GB code. 0 R/W RAiO TECHNOLOGY INC. 13/193 www.raio.com.tw
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