Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB ... - Keil

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Functional overview STM32L151xD STM32L152xD Figure 2. Clock tree Standby supplied voltage domain enable Watchdog LSI RC LSI tempo Watchdog LS RTC enable LSE OSC LSE tempo RTC LS LS LS LS 1 MHz LCD enable CK_LCD @V33 MSI RC level shifters @V DDCORE @V33 HSI RC level shifters @V DDCORE @V33 HSE OSC level shifters @V DDCORE @V33 1 MHz clock detector LS LS CK_USB48 CK_TIMTGO CK_APB1 CK_APB2 @V DDCORE ck_lsi ck_lse / 1,2,4,8,16 / 2,4,8,16 ck_msi ck_hsi ck_hse @V33 ck_pll PLL ck_pllin X 3,4,6,8,12 16,24,32,48 level shifters @V DDCORE HSE present or not usben and (not deepsleep) ck_usb = Vco / 2 (Vco must be at 96 MHz) timer9en and (not deepsleep) / 2, 3, 4 apb1 periphen and (not deepsleep) apb2 periphen and (not deepsleep) Clock source control System clock MCO AHB prescaler / 1,2,..512 if (APB1 presc = 1)x1 else x2 ADC enable not deepsleep not deepsleep not (sleep or deepsleep not (sleep or deepsleep) APB1 APB2 prescaler prescaler / 1,2,4,8,16 / 1,2,4,8,16 CK_ADC CK_PWR CK_FCLK CK_CPU / 8 CK_TIMSYS MS18583V1 1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz. 22/140 Doc ID 022027 Rev 6
STM32L151xD STM32L152xD Functional overview 3.5 Low power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 µs to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronisation. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. Doc ID 022027 Rev 6 23/140
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Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB ... - Keil

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