u-blox 6
u-blox 6
u-blox 6
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
4.3.1.1 Random Read Access<br />
Random read operations allow the master to access any register in a random manner. To perform this type of<br />
read operation, first the register address to read from must be written to the receiver (see Figure DDC Random<br />
Read Access). Following the start condition from the master, the 7-bit device address and the RW bit (which is a<br />
logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers with an<br />
acknowledge (logic low) to indicate that it is responsible for the given address. Next, the 8-bit address of the<br />
register to be read must be written to the bus. Following the receiver’s acknowledge, the master again triggers<br />
a start condition and writes the device address, but this time the RW bit is a logic high to initiate the read<br />
access. Now, the master can read 1 to N bytes from the receiver, generating a not-acknowledge and a stop<br />
condition after the last byte being read. After every byte being read, the internal address counter is<br />
incremented by one, saturating at 0xFF. This saturation means, that, after having read all registers coming after<br />
the initially set register address, the raw message stream can be read.<br />
DDC Random Read Access<br />
4.3.1.2 Current Address Read<br />
The receiver contains an address counter that maintains the address of the last register accessed, internally<br />
incremented by one. Therefore, if the previous read access was to address n (where n is any legal address), the<br />
next current address read operation would access data from address n+1 (see Figure DDC Current Address<br />
Read Access). Upon receipt of the device address with the RW bit set to one, the receiver issues an acknowledge<br />
and the master can read 1 to N bytes from the receiver, generating a not-acknowledge and a stop condition<br />
after the last byte being read.<br />
To allow direct access to streaming data, the internal address counter is initialized to 0xFF, meaning that<br />
current address reads without a preceding random read access return the raw message stream. The address<br />
counter can be set to another address at any point using a random read access.<br />
GPS.G6-SW-10018-A Public Release Page 10 of 201