Soft-Output Values Propagation through the Boolean Logic ... - Telfor

14th Telecommunications forum TELFOR 2006 Serbia, Belgrade, November 21-23, 2006
Soft-Output Values Propagation through the
Boolean Logic Circuits
Nikola Djuric, Member, IEEE
Abstract - The soft-decision decoding, of codes based on the
Boolean logics circuits and employed in magnetic recording
systems, has been considered in this paper. Simple and hardware
low-required approach for the soft-output value transmission
through the Boolean logic circuits is presented. Some
mathematical approximations have been used to employ the
soft-decision in AND, OR and XOR Boolean logics circuits
and consequently in maximum transition run (MTR) codes.
Keywords — soft-output value, soft-decision decoding, constrained
coding, magnetic recording systems, maximum transition
run code.
I. INTRODUCTION
HE well known Boolean logic circuits, such as AND,
TOR and XOR circuit are binary decision circuits. They
are found on so-called hard-decision basis, producing only
one type of information on their output: 0 or 1. In modern
decoding technique the soft-output value or soft-value has
been widely accepted as the essential information for the
proper decoder decisions [1].
The soft-value of the binary variable x is defined using
the log-likelihood ratio (LLR) as:
P(
x 0)
LLR ( x)
log ,
(1)
P(
x 1)
where log() is natural logarithm and P() is probability. The
sign of the LLR(x) corresponds to the hard-decision, while
its magnitude |LLR(x)| stands for the reliability of decision.
This new class of information, the decision reliability, is
highly valuable, since increases the available information
redundancy and produces the additional degree of decision
freedom. With variable soft-value, decoder instantly poses
information about its hard-decision and also the reliability
level about that decision. Consequently, this increases its
chances for the proper estimations.
The Boolean logic circuits are preferred in any kind of
hardware realization, because the present integrated circuit
technology makes Boolean logic circuits quite simple for
realization. Unfortunately, codes which are based on these
circuits, such as the well known maximum transition run
(MTR) codes [2], are fated on their hard-decisions.
Research in iterative decoding/detection [3], for applications
in magnetic recording, created a great interest among
researchers [4]. This technique assumes exchange of softvalues
among decoders/detectors, as their a prior informa-
N. Djuric is with the Faculty of Technical sciences, University of Novi
Sad, Serbia (phone: +381 21 6 350 805; fax: +381 21 475 05 72; e-mail:
ndjuric@uns.ns.ac.yu).
tion, which can be utilized to improve estimations in some
following iterations.
Therefore, in order to employ the Boolean logic circuits
in a soft-decision decoding fashion and consequently in an
iterative decoding scheme, the propagation of soft-values
trough the basic Boolean circuits has to be accomplished.
In this paper we present a simple method for the soft-value
forwarding through the Boolean logic circuits. Mathematical
approximations with hardware low-requirements have
been used to employ the LLR functionalities in AND, OR
and XOR circuits [5].
An approach for soft-value forwarding and soft-decision
decoding in Boolean circuits is presented in the Section II.
Utilization consequence of mathematical approximation is
described in Section III, while advantage and disadvantage
of this method, particularly in case of MTR codes, is presented
in Section IV. Finally, conclusions on the paper are
given in Section V.
II. AN APPROACH FOR THE SOFT-VALUE PROPAGATION
In case of Boolean NOT logic easily can be shown that:
P(
x 0) P(
x 1)
LLR( x)
log log LLR(
x),
(2)
P(
x 1) P(
x 0)
so, the propagation is accomplished by changing the sign
of the soft-value which enters into the Boolean NOT logic.
This approach can be also applied for the LLR of Boolean
AND logic output as:
P(
x1
AND x2
0)
LLR ( x1
AND x2)
log
, (3)
P(
x1
AND x2
1)
and, assuming statistical independency of binary variables
x 1 and x 2 , this LLR can be written as:
LLR(
x1
AND x2)
(4)
LLR(
x1 ) LLR(
x2
) LLL(
x1
) LLR(
x2
)
log( e e e
).
The LLR of Boolean OR logic circuit output can be expressed
as:
P(
x1
OR x2
0)
LLR ( x1
OR x2)
log
, (5)
P(
x1
OR x2
1)
while assuming statistical independency, it is:
LLR(
x1
OR x2)
(6)
LLR(
x1 ) LLR(
x2
) (
LLL(
x1
) LLR(
x2
))
log( e e e
).
Finally, the LLR of Boolean XOR logic output is:
P(
x1
XOR x2
0)
LLR ( x1
XOR x2)
log
, (7)
P(
x1
XOR x2
1)
and, when statistical independency was assumed, it can be
represented as:
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LLR(
x ) LLR(
x )
1
2
1
e e
LLR(
x1
XOR x2)
log
. (8)
LLR(
x1
) LLR(
x2
)
e e
Unfortunately, effortless propagation of the soft-values
in presented approach can not be achieved using equations
(4), (6) and (8), since hardware realization of the log() and
exp() functions, in digital systems, is not so easy task. For
that reason, we have to employ some approximations with
low-required hardware demands.
III. SUGGESTED APPROXIMATIONS
In case of the LLR of Boolean AND logic, the following
approximation [5]:
LLR app ( x1 AND x2)
max[ LLR(
x1),
LLR(
x2)],
(9)
simplifies the hardware realization of the soft-output values
propagation through the circuits.
This approximation in certain degree accompanies the
exact expression, but some deviation appears when LLR of
both AND operands increases, as shown in Fig. 1.
10
5
0
log[e LLR(x1) + e LLR(x2) + e LLR(x1)+LLR(x2) ]
-5
5
0
LLR(x 2
)
5
4
3
2
1
0
5
0
LLR(x 2
)
-5
-5
0 2 4
LLR(x ) 1
LLR(x 1
AND x 2
) - LLR app
(x 1
AND x 2
)
-5
0
LLR(x 1
)
5
LLR(x 2
)
4
2
0
-2
-4
5
0
LLR(x ) 2
4
2
0
-2
max[LLR(x 1
), LLR(x 2
)]
-5
0 2 4
LLR(x ) 1
LLR(x 1
AND x 2
) - LLR app
(x 1
AND x 2
)
-4
-4 -2 0 2 4
LLR(x 1
)
Fig. 1 LLR of Boolean AND logic and its approximation
Disagreement is not critical because in moments when it
appears the output result obtained by the exact expression
and its approximation is known with sufficiently high reliability,
which is acceptable for the proper decoder estimation.
Simple hardware realization of the LLR of Boolean OR
logic is possible using approximation:
LLR app ( x1 OR x2)
min[ LLR(
x1
), LLR(
x2)].
(10)
while deviation between approximation and the exact expression
is shown in Fig. 2.
It can be observed that disagreement appears when LLR
of both Boolean OR operands decreases, but in those moments
Boolean logic output result is already well known.
Finally, using approximation as fallowing one:
LLL app ( x1
XOR x2)
sign[
LLR(
x1)]
sign[
LLR(
x2)]
(11)
min[ LLR(
x1
), LLR(
x2)],
simple propagation is possible through the Boolean XOR
circuit. Deviation of the approximation is show in Fig. 3.
log[(1 + e LLR(x1)+LLR(x2) ) / (e LLR(x1) + e LLR(x2) ) ]
4
2
0
-2
-4
-4
5
5
0
0
-4 -2 0 2 4
LLR(x
-5
2
) -4 -2 0 2 4
LLR(x
-5
LLR(x 1
)
2
)
LLR(x 1
)
1
0.5
0
-0.5
LLR(x 1
XOR x 2
) - LLR app
(x 1
XOR x 2
)
sign[LLR(x 1
)] sign[LLR(x 2
)] min[LLR(x 1
), LLR(x 2
)]
2
-2
-1
5
0
0 2 4
-4
-5 -2 -4 LLR(x ) -4 -2 0 2 4
LLR(x 1
)
LLR(x ) 1
LLR(x 2
)
4
2
0
-2
4
2
0
LLR(x 1
XOR x 2
) - LLR app
(x 1
XOR x 2
)
Fig. 3 LLR of Boolean XOR logic and its approximation
The small degree of deviation appears when both XOR
operands have similar LLR values, but when this occur the
Boolean XOR logic output result is already well known so
the exact reliability is not highly important.
IV. MTR SOFT-DECISION DECODING
With suggested LLR implementation, the soft-output information
can be spread through the basic Boolean circuits
preserving hardware complexity at the same level. Similar
logic circuits, but with the LLR functionalities, can be utilized
to make possible the soft-decision MTR decoding and
to employ MTR codes in iterative decoding schemes [6].
MTR codes can be described as MTR (k 1 , j) where k 1 is
transition run constraint, and j is usual RLL constraint [2].
In a case of rate 4/5 (k 1 = 2, 8) MTR code, hardware realization
which provides simple and low-cost realization, is
shown in Fig. 4.
x0 x1 x2 x3
y0
y0 y1 y2 y3
y4
x0
5
-log[e -LLR(x1) + e -LLR(x2) + e -[LLR(x1)+LLR(x2)] ]
4
min[LLR(x 1
), LLR(x 2
)]
x1
0
2
y1
x2
0
y2
-5
-2
-10
5
0
LLR(x ) 2
-5
-5
0
LLR(x 1
)
5
-4
5
0
LLR(x ) 2
-5
-5
0
LLR(x 1
)
5
y3
x3
0
LLR(x 1
OR x 2
) - LLR app
(x 1
OR x 2
)
4
LLR(x 1
OR x 2
) - LLR app
(x 1
OR x 2
)
y4
-1
-2
-3
-4
-5
5
0
LLR(x 2
)
-5
0 2 4
LLR(x 1
)
LLR(x 2
)
2
0
-2
-4
-4 -2 0 2 4
LLR(x 1
)
Fig. 2 LLR of Boolean OR logic and its approximation
MTR Encoder
MTR Decoder
Fig. 4 Rate 4/5 (k 1 = 2, 8) MTR code implementation
Using logic circuits with LLR functionalities, described
by equation (2), (9), (10) and (11), iterative decoding utilization
of MTR codes is possible [7], as shown in Fig. 5.
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y
Message
SOVA
Soft-decision
MTR decoder
1D Passing
1 Soft-decision LLR MESS.PASS.
1 D MTR coder N iter
LLR SOVA LLR MTR
N iter
LDPC Decoder
-1 -> 1
+1 -> 0
LLR MESS.PASS.
Fig. 5 Iterative decoding
Info. bit
Decoder
LDPC–MTR concatenation was performed over E 2 PR4
partial response magnetic recording channel [8], using rate
R = 0.96 LDPC, of length N = 4732 with M = 169 parity
`bits and with column-weight 3 [9], as an outer and rate
4/5 MTR (k 1 = 2, 8) as an inner encoding code.
Channel detection has been performed by optimum softoutput
Viterbi detector (SOVA) [1], while LDPC decoding
by the message-passing algorithm [10].
In this simulation scenario the feedback from messagepassing
to the SOVA detector, has been incorporated, using
the soft-output MTR encoder. Now, the algorithms can
exchange the soft-output values between each other, trying
to improve their estimations from the previous iterations.
Unfortunately, as can be seen from the Fig. 4, bits of the
MTR decoder output codeword are:
x y y y y y y y
0
1
2
3
1
x y
2
3
0
3
0
x y y y y y
0
2
2
4 .
x y y y
3
0
0
4
2
3
i
(12)
LLR of each of them is highly conditioned with several
decoder input bits, which means that soft-output information,
which propagates through the MTR modul, very soon
becomes statistically dependent. Therefore, with increased
number of iterations statistical independency in equations
(4), (6) and (8) can not be strictly assumed, and thus equations
(9), (10), and (11) can not precisely describe the exact
LLR expressions of the MTR Boolean logic circuits.
Simulation results are depicted in Fig. 6.
BER
10 0 LDPC - MTR codes concatenation over E 2 PR4 channel
10 -1
Uncoded case
Niter = 0
MTR
Niter = 2
soft-decision{
Niter = 4
Niter = 6
10 -2
10 -3
10 -4
10 -5
10 -6
6 7 8 9 10 11 12
SNR = 10log(Eb/No) [dB]
Fig. 6 Iterative decoding of LDPC–MTR codes
The promising soft-decision MTR implementation with
increased number of iteration have a similar decoding gain
of 1.7dB, around BER = 10 -5 , far all iterations, comparing
to uncoded case. Unfortunately, when the number of iterations
is increased there is no additional coding gain, comparing
with the first iteration.
Obtained results are not so un-expected, since extensive
dependencies are present in MTR codeword bits, resulting
with not so reliable soft-output information. Consequently,
such unreliable information can not help SOVA and message-passing
algorithms to improve their decisions in following
iterations.
V. CONCLUSION
Simple approach for the soft-output values propagation
through the basic Boolean logic circuits was considered.
In order to employ method with hardware low demands,
a few effortless mathematical approximations have been
used. It is shown that fast and effective propagation, of the
soft-output information, can be obtained by utilizing LLR
algebra in basic Boolean logic circuits.
Consequently, the soft-decision MTR decoder was constructed
using logic circuits with LLR functionalities. Such
implementation makes possible the MTR codes utilization
in iterative decoding schemes. In one of them, we consider
a case when LDPC acts as an outer and MTR as an inner
code, over E 2 PR4 magnetic recording channel. Using the
soft-output MTR decoding, 1.7dB decoding gain has been
obtained for BER = 10 -5 , comparing to the uncoded case.
Unfortunately, with increased number of iterations there
is no additional coding gain, since high statistical dependency
is present in decoder output codeword. In such situation
the suggested method can not accurately describe the
exact LLR expressions of the basic Boolean logic circuits.
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