Open NAND Flash Interface Specification - Micron

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9 Figure 3 48-pin TSOP/WSOP pinout for 16-bit data access 48-pin TSOP and 48-pin WSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 R R R R/B3_n R/B2_n R/B1_n R/B0_n RE_n CE0_n CE1_n R Vcc Vss CE2_n CE3_n CLE ALE WE_n WP_n VSP3 R R R R VssQ IO15 IO14 IO13 IO7 IO6 IO5 IO4 IO12 VccQ VSP1 Vcc Vss VSP2 VccQ IO11 IO3 IO2 IO1 IO0 IO10 IO9 IO8 VssQ
2.2. LGA-52 Pad Assignments Figure 4 defines the pad assignments for devices using 52-pad LGA packaging with 8-bit data access. An option is specified for two independent 8-bit data buses. Figure 5 defines the pad assignments for devices using 52-pad LGA packaging with 16-bit data access. The physical dimensions of the package are 12mmx17mm or 14mmx18mm. Figure 6 defines the pad spacing requirements for the 52-pad LGA package for both package dimensions. These LGA packages do not support the source synchronous data interface. 8 7 6 5 4 3 2 1 0 R/B1_ 1_n CE1_ 1_n A B C D E F G H J K L M N R/B1_ 0_n CE0_ 0_n CLE _0 CE1_ 0_n VDDi R R VssQ R Vcc Vss RE_0 _n CE0_ 1_n CLE _1 ALE _0 RE_1 _n ALE _1 R/B0_ 1_n R/B0_ 0_n WE_0 _n WE_1 _n Vss WP_0 _n Figure 4 LGA pinout for 8-bit data access 10 IO7 _1 WP_1 _n IO0 _0 IO0 _1 IO7 _0 IO1 _0 IO6 _1 IO6 _0 IO2 _0 IO1 _1 IO5 _0 IO3 _0 IO5 _1 IO4 _0 Vss IO2 _1 Vcc VssQ VccQ IO4 _1 IO3 _1 VccQ R R R R R OA OB OC OD OE OF
Page 1 and 2: Open NAND Flash Interface Specifica
Page 3 and 4: Table of Contents 1. Introduction .
Page 5 and 6: 7.1.8. Page Program and Page Cache
Page 7 and 8: 1.4. Definitions, abbreviations, an
Page 9 and 10: 1.4.1.21. Uncorrectable Bit Error R
Page 11 and 12: elow shows the general layout for e
Page 13: Ssync R R R R/B3_n R/B2_n R/B1_n R/
Page 17 and 18: 1 mm pad diameter A B C D E F G H J
Page 19 and 20: Note that WE_n is located at ball H
Page 21 and 22: 0.45 mm ball diameter post reflow 0
Page 23 and 24: A B C D E F G H J K L M N P R T U 1
Page 25 and 26: 2.5. Signal Descriptions Table 2 pr
Page 27 and 28: does not implement that signal. Any
Page 29 and 30: Signal Name M/O/R TSOP / WSOP Async
Page 31 and 32: 2.6. CE_n Signal Requirements If on
Page 33 and 34: 2.9. AC Overshoot/Undershoot Requir
Page 35 and 36: Parameter Symbol Test Conditions Mi
Page 37 and 38: capacitance may be used, or the typ
Page 39 and 40: 2.16.2. R/B_n and SR[6] Relationshi
Page 41 and 42: A block is the smallest erasable un
Page 43 and 44: Multi-plane Multi-plane Lower Bit X
Page 45 and 46: 3.2.2. Host Requirements The host s
Page 47 and 48: 3.4. Discovery and Initialization 3
Page 49 and 50: 4. Data Interface and Timing 4.1. D
Page 51 and 52: CE_n ALE CLE W/R_n CLK Source Synch
Page 53 and 54: � RE_n / W/R_n shall be set to on
Page 55 and 56: Parameter Description tADL 3 ALE to
Page 57 and 58: Figure 22 EZ NAND Output Reference
Page 59 and 60: Table 23 Asynchronous Timing Modes
Page 61 and 62: Table 24 Asynchronous Timing Modes
Page 63 and 64: tITC 1 Interface and Timing Mode Ch
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Description R_pulldown R_pullup Des
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Output Impedance Maximum Minimum Un
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The testing conditions that shall b
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If timing mode 0 is selected, then
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tDSS 0.2 — 0.2 — 0.2 — 0.2
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CLE CE_n 4.3.1.2. Address Latch Tim
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4.3.1.4. Data Output Cycle Timings
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CLE CE_n 4.3.1.6. Read Status Timin
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4.3.2. Source Synchronous For the c
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4.3.2.3. Data Input Cycle Timings D
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4.3.2.4. Data Input Cycle Timings,
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CE_n CLE ALE CLK W/R_n DQS DQ[7:0]
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CE_n CLE ALE CLK W/R_n DQS DQ[7:0]
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4.3.2.7. Satisfying Timing Requirem
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4.4. Command Examples 4.4.1. Asynch
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Figure 42 shows an example of Chang
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CLK CE_n CLE ALE W/R_n DQ[7:0] DQS
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CLK CE_n CLE ALE W/R_n DQ[7:0] DQS
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5. Command Definition 5.1. Command
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Type Opcode Vendor Specific 02h - 0
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CE_n CLE ALE WE_n RE_n IOx 85h Figu
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5.3. Reset Definition The Reset fun
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Cycle Type DQ[7:0] SR[6] 5.6. Read
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Figure 56 Read ID command using sou
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5.7.1. Parameter Page Data Structur
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Byte O/M Description 129-130 M Asyn
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Bit 3 when set to one indicates tha
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5.7.1.8. Byte 44-63: Device model T
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5.7.1.23. Byte 108-109: Block endur
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Bit 2 indicates whether the target
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us. As an example, if two LUNs are
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5.7.1.6. Byte 512-767: Redundant Pa
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Byte O/M Description Revision infor
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Bytes Value 0-15 UID 16-31 UID comp
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Status Register bit Composite statu
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Figure 62 Read Status command using
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program and erase operations. For E
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Cycle Type DQx SR[6] CMD 00h ADDR C
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Cycle Type DQx SR[6] As defined for
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Figure 67 defines the Read Cache (S
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Cycle Type DQx SR[6] CMD 80h ADDR C
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Cycle Type DQx SR[6] Cycle Type DQx
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C1-C2 Column address of the startin
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R1-R3 B Row address of the page to
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Page 155 and 156:
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5.20. Change Read Column Definition
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5.22. Change Write Column Definitio
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5.24. Set Features Definition The S
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5.25. Get Features Definition The G
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5.26.2. I/O Drive Strength This set
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60h CMD D1h CMD Multi-plane Op 1 F
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R1B-R3B D0B-DnB Row address for pag
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The row addresses for all source pa
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6.5. Multi-plane Block Erase Figure
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Cycle Type DQx SR[6] B CMD 30h tWB
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7. Behavioral Flows 7.1. Target beh
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7.1.3. Idle Read states T_Idle_Rd W
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T_CRE_RowAddrWait Wait for a row ad
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T_RST_LUN_AddrWait Wait for an addr
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T_RPP_ReadParams The target perform
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T_PP_LUN_Execute The target perform
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T_PP_RowChg_Addr Store the address
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7.1.10. Read command states T_RD_Ex
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7.1.11. Set Features command states
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7.1.14. Read Status Enhanced comman
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L_Idle_TargetRequest If Target indi
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7.2.4. Status states L_Status_Execu
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interleaving is supported. 1. Uncon
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L_RD_ArrayRead_Cont 1. Read of requ
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3. Command cycle 15h (cache program
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1. Unconditional � L_Idle L_PP_Ca
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} while(scanf("%x", &data_in) == 1)
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C. DEVICE SELF-INITIALIZATION WITH
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The following figures detail the te
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Cycle Type DQx R/B_n CMD 80h 212 Fi
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Cycle Type DQx R/B_n Cycle Type DQx
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Cycle Type DQ[7:0] R/B_n 216 IDLE F
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F. EZ NAND: END TO END DATA PATH PR
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Open NAND Flash Interface Specification - Micron

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