Open NAND Flash Interface Specification - Micron

Signal
Name
Input /
Output
Description
WE_x_n I Write Enable
The Write Enable signal controls the latching of input data in the
asynchronous data interface. Data, commands, and addresses are latched
on the rising edge of WE_x_n. This signal shares the same pin as CLK_x
in the source synchronous data interface.
CLK_x_t I Clock
The Clock signal is used as the clock in the source synchronous data
interface. This signal shares the same pin as WE_x_n in the
asynchronous data interface.
CLK_x_c I Clock Complement
WP_x_n
IO0_0 –
IO7_0
(DQ0_0 –
DQ7_0)
This signal is reserved for future use.
I Write Protect
The Write Protect signal disables Flash array program and erase
operations. See section 2.17 for requirements.
I/O I/O Port 0, bits 0-7
The I/O port is an 8-bit wide bidirectional port for transferring address,
command, and data to and from the device. Also known as DQ0_0 –
DQ7_0 for the source synchronous data interface.
DQS_x_t I/O Data Strobe
The data strobe signal that indicates the data valid window for the source
synchronous data interface.
DQS_x_c I/O Data Strobe Complement
IO8 –
IO15
IO0_1 –
IO7_1
(DQ0_1 –
DQ7_1)
This signal is reserved for future use.
I/O I/O Port 0, bits 8-15
These signals are used in a 16-bit wide target configuration. The signals
are the upper 8 bits for the 16-bit wide bidirectional port used to transfer
data to and from the device.
I/O I/O Port 1, bits 0-7
The I/O port is an 8-bit wide bidirectional port for transferring address,
command, and data to and from the device. These pins may be used as
an additional 8-bit wide bidirectional port for devices that support two
independent data buses. Also known as DQ0_1 – DQ7_1 for the source
synchronous data interface.
VSP_x Vendor Specific
The function of these signals is defined and specified by the NAND
vendor. Devices shall have an internal pull-up or pull-down resistor on
these signals to yield ONFI compliant behavior when a signal is not
connected by the host. Any VSP signal not used by the NAND vendor
shall not be connected internal to the device.
R Reserved
These pins shall not be connected by the host.
RFT Reserved for Test
These pins shall not be connected by the host.
Table 2 Signal descriptions
Table 3 provides the signal mapping to pin/pad/ball for each package type listed within the ONFI
specification. These signal mappings are required if the packages listed in this specification are
implemented. The “Async Only” signal mappings apply to packages where the device is not
source synchronous capable. When the device is source synchronous capable, the “Src Sync”
signal mappings shall be used. If a signal is marked as “na” then the corresponding package
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