Open NAND Flash Interface Specification - Micron

command transfers, the host may place any value on the upper 8-bits of the data bus. During
address transfers, the host shall set the upper 8-bits of the data bus to 00h.
2.16. Ready/Busy (R/B_n) Requirements
2.16.1. Power-On Requirements
Once VCC and VccQ reach the VCC minimum and VccQ minimum values, respectively, listed in
Table 5 and power is stable, the R/B_n signal shall be valid after RB_valid_Vcc and shall be set
to one (Ready) within RB_device_ready, as listed in Table 11. R/B_n is undefined until 50 µs
has elapsed after VCC has started to ramp. The R/B_n signal is not valid until both of these
conditions are met.
Parameter Raw NAND EZ NAND
RB_valid_Vcc 10 µs 250 µs
RB_device_ready 1 ms 2 ms
Table 11 R/B_n Power-on Requirements
During power-on, VccQ shall be less than or equal to Vcc at all times. Figure 15 shows VccQ
ramping after Vcc, however, they may ramp at the same time.
VccQ
Vcc
R/B_n
Vcc ramp
starts
>= 0 µs
(min)
50 µs
(min)
Vcc =
Vcc_min
RB_valid_Vcc
VccQ =
VccQ_min
Figure 15 R/B_n Power-On Behavior
Ready/Busy is implemented as an open drain circuit, thus a pull-up resistor shall be used for
termination. The combination of the pull-up resistor and the capacitive loading of the R/B_n
circuit determines the rise time of R/B_n.
33
RB_device_ready
Undefined
Reset (FFh)
is issued