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ks0073 34com / 60seg driver & controller for dot matrix lcd

ks0073 34com / 60seg driver & controller for dot matrix lcd

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KS0073<br />

34COM / 60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD<br />

(Table 6. continued)<br />

Instruction<br />

Set<br />

CGRAM<br />

Address<br />

Instruction Code<br />

RE<br />

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />

Description<br />

Set CGRAM address in address<br />

0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0<br />

counter.<br />

Execution<br />

Time<br />

(fosc<br />

270 kHz)<br />

39 µs<br />

Set<br />

SEGRAM<br />

Address<br />

1 0 0 0 1 X X AC3 AC2 AC1 AC0<br />

Set SEGRAM address in<br />

address counter.<br />

39 µs<br />

Set<br />

DDRAM<br />

Address<br />

0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address<br />

counter.<br />

39 µs<br />

Set<br />

Scroll<br />

Quantity<br />

Set the quantity of horizontal <strong>dot</strong><br />

1 0 0 1 X SQ5 SQ4 SQ3 SQ2 SQ1 SQ0<br />

scroll.<br />

39 µs<br />

Read<br />

Busy Flag<br />

and Address<br />

Write<br />

Data<br />

Read<br />

Data<br />

X 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0<br />

X 1 0 D7 D6 D5 D4 D3 D2 D1 D0<br />

X 1 1 D7 D6 D5 D4 D3 D2 D1 D0<br />

Can be known whether during<br />

internal operation or not by<br />

reading BF.<br />

The contents of address counter<br />

can also be read.<br />

(BF = “1”: busy state,<br />

BF = “0”: ready state)<br />

Write data into internal RAM<br />

(DDRAM/CGRAM/SEGRAM)<br />

Read data from internal RAM<br />

(DDRAM/CGRAM/SEGRAM)<br />

0 µs<br />

43 µs<br />

43 µs<br />

* NOTE: When an MPU program with Busy Flag (DB7) checking is made, 1/2Fosc is necessary <strong>for</strong> executing<br />

the next instruction by the falling edge of the ‘E’ signal after the Busy Flag (DB7) goes to “Low”.<br />

“X” : Don't care

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