LinkSwitch-HP Family - Codico

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LinkSwitch-HP Layout Considerations for eSIP-7C Package Figure 12 is the layout for a 30 W adapter shown in the schematic Figure 11. An eSIP-7C package is used as indicated by the suffix in LNK6766E which allows the use of a stand-up heat sink. The mounting pin for the heat sink should be electrically isolated. It can be seen that the primary return trace wraps around the LinkSwitch-HP device which acts as a shield around the critical external control related components of LinkSwitch-HP. These components include R7, R8, R19, R20 and C5, C8, C20. Of particular importance is placing the bypass capacitor C5 and COMPENSATION pin noise filter capacitor C8 as close as possible to SOURCE pin with very short trace lengths to COMPENSATION and BYPASS pins as done in the layout above. The ground trace wrap, tight layout and single point grounding to SOURCE pin of these components avoids having noise related issues during peak loads or during line transient such as surge or ESD events. Another consideration for ESD and line surge is the primaryside termination of the Y capacitor. The Y capacitor C18 should be tied to the positive terminal of the bulk capacitor C2 in order to route the potential of high currents away from the more sensitive primary return traces. Because of the tight layout common to adapter applications, this design uses triple insulated wire and flying leads for output winding termination to avoid secondary arcing to core during ESD events. The trace connecting the drain to transformer should be very short and the primary clamp circuitry should be grouped together and away from the more sensitive components. The bias winding return and return of bias capacitor C6 should be routed separately to the negative terminal of the input capacitor C2 away from SOURCE pin. The secondary rectifying loop that includes the secondary winding, the output diode D8, and the first output capacitor C13 should be as tight as possible to minimize adding series inductance which can reduce high load efficiency and degrade the quality of regulation. Figure 12. Layout for 30 W Adapter Using a eSIP-7C Package. 10 Rev. A 07/12 www.powerint.com
LinkSwitch-HP Layout Considerations for eDIP-12B package Quick Design Checklist The schematic in Figure 13 is an example of LinkSwitch-HP used in a dual output LCD monitor supply using eDIP-12B package. In this design the exposed metal tab on the topside of package is left open (no heat sink). The SOURCE pins of LinkSwitch-HP provide heat sinking through connection to the source copper pad of PCB. This technique is adequate for device dissipation up to 0.85 W (1/2 square inch of copper area required). The layout guidelines described for eSIP-7C are the same for eDIP-12B with an added consideration about sensitive component layout. The return referenced components C4, C8, C16, R9, R7 must be placed directly under the LinkSwitch-HP BR1 DF06M package as shown in Figure 14. This requires that these 600 V particular components be SMD type as this allows an ideal noise-immune layout. Output Power Table Assumptions L1 10 mH • 12 V output C1 • Schottky rectification 100 nF 310 VAC • 82% efficiency • V OR = 135 V • K P = 0.4 for 85-265 VAC input and K P = 0.6 F1 RT1 for 195-265 VAC 2 A 5 Ω t O input 90 - 265 • V MIN = 100 V for 85-265 VAC input and V MIN = 250 V for J1-3 J1-1 195-265 VAC input • 0.85 W device dissipation for open frame designs with PCB heat sink VAC C2 47 µF 450 V All LinkSwitch-HP designs should be verified on the bench particularly for specified worst-case stress conditions. The following set of tests are strongly recommended: C9 1 nF 250 VAC 1/8 W 200 V 1. Maximum drain voltage – Verify that VDS does not exceed 675 V for LNK677X series 6 and 12600 V for LNK6X6X series. This gives a 50 V margin for design variations. D3 30BQ100PBF R1 R2 R3 2. Under 3 kΩ all 100 conditions, Ω 100 Ω the maximum Drain current R12 should be 1% 1% 10 Ω C15 below the specified absolute maximum ratings. 1% 470 pF 1/8 W 200 V 3. Thermal check – At rated maximum output power, minimum VR1 input P6KE130A C3 voltage and maximum ambient 7,8 temperature, verify that 130 V 10 nF 630 V the maximum allowed temperature is not exceeded D4 for any B340LB-13-F component in the design. Of particular importance is R4 9,10 checking the 20 temperature Ω rise of the major power conversion 1% 3 components such as transformer, output D2 diodes, input BAV21WS- C6 bridge, primary D1 clamp circuit and LinkSwitch-HP. 7-F 22 µF Under the DL4937 25 V R5 stated conditions above, LinkSwitch-HP tab temperature 6.98 kΩ 5 1 1% should not exceed 110 °C. 1/8 W LinkSwitch-HP U3 LNK6774V C4* *Optional D S R6 23.2 kΩ 1% 1/16 W PD BP CONTROL CP FB R7 100 kΩ 1% 1/16 W C7 100 nF 25 V T1 EF25 C16 10 pF 50 V C8 100 pF 50 V R8 46.4 kΩ 1% 1/16 W R9 10.5 kΩ 1% 1/16 W R10 10 Ω 1% C10 470 pF PI-6860-072412 L2 Ferrite Bead (3.5 × 4.45 mm) C13 820 µF 6.3 V C5 4.7 µF 10 V PI-6860-072412 C11 220 µ 35 V C14 820 µ 6.3 V Figure 13. 17 W LCD Monitor Supply (+18 V, +5 V). Figure 14. Layout for LCD Monitor Supply Using eDIP-12B Package. www.powerint.com 11 Rev. A 07/12
Page 1 and 2: LinkSwitch-HP Family Energy Efficie
Page 3 and 4: LinkSwitch-HP Pin Functional Descri
Page 5 and 6: LinkSwitch-HP Auto-Restart On-Time
Page 7 and 8: LinkSwitch-HP SW V FB V PDTHACR 3.4
Page 9: LinkSwitch-HP The transient load re
Page 13 and 14: LinkSwitch-HP Parameter Symbol Cond
Page 15 and 16: LinkSwitch-HP Parameter Symbol Cond
Page 17 and 18: LinkSwitch-HP Figure 15. Duty Cycle
Page 19 and 20: LinkSwitch-HP Typical Performance C
Page 21 and 22: LinkSwitch-HP eDIP-12B (V Package)
Page 23 and 24: LinkSwitch-HP www.powerint.com 23 R

LinkSwitch-HP Family - Codico

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