Signetics Programmable Logic Devices - Al Kossow's Bitsavers

Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
By placing a (-) Don't Care in each input bex
you are specifying that the True and Complement
fuses are programmed on each Control
Gate, thus permanently dedcating the Be and
B, pins as outputs. By placing a (0) in all input
boxes for B2 - Bs, you are specifying that beth
True and Complement fuses are intact. This
causes a low (0) to be forced on half of the
Control Gate inputs, guaranteeing the output of
the Control Gate will be low (0). When the
Control Gate outputs are low (0), the 3-State
buffer is inactive and the ~ - B9 pins are
enabled as inputs. All Bx pin directions can be
controlled in this manner.
ACTIVE DIRECTION CONTROL
Sometimes it is necessary to be able to actively
change the direction of the Bx pins without permanently
dedicating them. Some applications
which require this include 3-State bus enable,
multi-function decoding, etc. This can easily be
done by programming the Control Gate to
respond to one or more input pins. ltis only necessaryto
select which Ix and Bx pins will control
the pin directions and the active level HIGH (H)
or LOW (L) thatwill be used. The PLUS 153 Program
Table in Figure 15 shows the method of
controlling Be - B9 with 17. When 17 is LOW (L).
pins Be - Bs are outputs; when 17 is HIGH (H),
pins Be - Bs are inputs. Note that by programming
all other Ix and Bx pins as DON'T CARE
(-), they are permanenHy disconnected from
control of Bx pin direction.
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T
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R
B(I)
ffl 1'";'0- 10 1 ~
M 7 6
• • I 3
- 11:1- ~ • 1 0 9 I • 8 7 6 I • 111:1 4 3 1 0
-IL-:-+++--r-:-t-=-H""''''''-+-+--+-+--t--t-i-t-H
II: 01 ~ I!ZI '" -'Ir
0 I I I
~ _ I F ~ F ~ 101 a - ;0 -11-=-f---+-+--j-+-+-+-t-+--t---1~t----t--i-t---t---t-H
1 I I I
'" I~~ I I;; g 11-':"'-+--+--4~+--+-I-+-+-t-+--i-+--+-t-+-i-t---t---;
I 1 I
~ -}'=~~~---~~+-+-+-4-~-t-+~-1--r-t-t-i-i-~-t-t-i-i
•
3
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~: ~
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~ I •
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II: I 0 '" -' I
8 ~I - - - ~
it: "'I ~
•
30
! ~ ~ ~
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D. L
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01 L
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DO L
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1
PIN
• ,. 7 "
31
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09 L - -I 1
I
D8 L
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07 L
1 I
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D6 L
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1
os L
1 I
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D4 L
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D3 L
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AND
• • • 3 • 1 " , . 17
POLARITY
I I I I I I I
OR
B(O)
9 8 I 7 6 5 4 I 3 2 1 0
I I
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I I I I I
I I I I I
~J
NOTES:
1. The FPLA is shipped with all links inlact. Thus a
background of entries corresponding 10 stales of
virgin links exists in the table, shown BLANK for
darity.
2. Unused I and 8 bits in the AND array are normally
programmed Don't Care (-).
3 Unused product terms can be left blank.
I
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Figure 15. Active Control of Bo - 8, Using 17 Active Low (L)
Janumy 1990
19