Signetics Programmable Logic Devices - Al Kossow's Bitsavers

Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
SEQUENTIAL LOGIC
CONSIDERATIONS
The PLUS405, PLUS105 and PLC42VA12
represent significant increases in complexity
when compared to the combinatorial logic
devices previously discussed. By combining
the AND/OR combinatorial logic with clock
output flip-flops and appropriate feedback,
Signetics has created the first family of totally
flexible sequential logic machines.
The PLUS405(Programmable Logic Sequencer)
is an example of a high-order machine
whose applications are many. Application
areas for this device include VRAM, DRAM,
Bus and LAN control. The PLUS405 is fully
capable of performing fast sequential operations
in relatively high-speed processor
systems. By placing repetitive sequential operations
on the PLUS405, processor overhead is
reduced.
The following pages summarize the PLUS405
architecture and features.
Sequencer Architecture
The PLUS405 Logic Sequencer is a programmable
state machine, in which the output is a
function of the present state and the present
input.
With the PLUS405, a user can program any logic
sequence expressed as a series of jumps
between stable states, triggered by a valid input
condition (I) at clock time (t). All stable states
are stored in the State Register. The logic output
of the machine is also programmable, and
is stored in the Output Register. The PLUS105
is a subset of the PLUS405.
Clocked Sequence
A synchronous logic sequence can be represented
as a group of circles interconnectedwith
arrows. The circles represent stable states,
labeled with an arbitrary numerical code
(binary, hex, etc.) corresponding to discrete
states of a suitable register. The arrows represent
state transitions, labeled with symbols
denoting the jump condition and the required
change in output. The number of states in the
sequence depends on the length and complexity
of the desired algorithm.
ClOCK----------.--------------,
1-
COMBIN.
LOGIC
0= "'PUT
o = PRESENT STATE
o = NEXT STATE
o = NEXT OUTPUT
Figure 17. Basic Architecture of PLS105 FPLS. I, P, N, and F are Multi-line
Paths Denoting Groups of Binary Variables Programmed by The User.
Figure 18. Typical State Diagram.
1, -3 Are Jump Conditions Which
Must be Satisfied Before Any
Transitions Take Place. Fr Are
Changes in Output Triggered by 1m,
and Stored in The Output Register.
State Transitions a -> band c -> d
Involve No Output Change.
Figure 19. Typical State Transition
Between Any Two States of Figure
18. The Arrow Connecting the Two
States Gives Rise to a Transition
Term Tn. I is the Jump Condition.
January 1990
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