Signetics Programmable Logic Devices - Al Kossow's Bitsavers

Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
Figure 22. Typical AND Gate Coupled to (I) and (P) Inputs.
If at Least One Link Pair Remains Intact, Tn is Unconditionally Forced Low .
...)J,..
",Jj,..
1-0- T--D- D-
Figure 23. Choice of Input Polarity Coupling to a Typical
AND Gate. With Both Links Open, (I) is Logically Don't Care.
Input Buffers
16extemal inputs (1m! and 6 internal inputs (Ps),
fed back from the State Register, are combined
in the AND array through two sets of Truel
Complement (TIC) buffers. There are a total of
22 TIC buffers, all connected to multi-input
AND gates via fusible links which are initially
intact.
Selective fusing of these links allows coupling
either True, Complement, or Don't Care values
of (1m! and (Ps).
Figure 24. Typical Transition Terms
Involving Arbitrary Inputs and State
Variables. All Remaining Gate Inputs
Are Programmed Don't Care. Note
That T 2 Output is Slate Independent.
January 1 990
"AND" Array
State jumps and output changes are triggered
at clock time by valid transition terms Tn. These
are logical AND functions of the present state
(P) and the present input (I).
The PLUS 105 AN D Array contains a total of 48
AND gates. Each gate has 45 inputs - 44
connected to 22 TIC input buffers, and 1 dedicated
to the Complement Array. The outputs of
all AND gates are propagated through the OR
Array, and used at clock time (t) to force the
contents of the State Register from (P) to (N).
they are also used to control the Output
Register, so that the FPLS 8-bit output F, is a
function of the inputs and the present state. The
PLUS405 contains 64 AND gates in its' AND
array.
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