Xilinx - Design Reuse Methodology for ASIC and FPGA Designers.pdf

12Figure 4 - Zero Delay Clock Management. Multiple DLLs facilitate precise generation of zerodelayclocks both inside and outside the FPGA for highest chip-to-chip speedsPhase-Locked LoopWhile designed for the same basic functions, the PLL uses a different architecture to accomplishthe task. As shown in Figure 5, the fundamental difference between the PLL and DLL is that,instead of a delay line, the PLL uses a programmable oscillator to generate a clock signal thatapproximates the input clock CLKIN. The control logic, consisting of a phase detector and filter,adjusts the oscillator phase to compensate for the clock distribution delay.The PLL control logic compares the input clock to the feedback clock CLKFB and adjusts theoscillator clock until the rising edge of the input clock aligns with the rising edge of the feedbackclock. The PLL then “locks”. The Altera FLEX 20KE is an example of a FPGA architecture thatcontains a clock management system with phase-locked lock (PLL).Figure 5 - Phase-Locked Loop Block DiagramGuideline – If a phase-locked loop (PLL) is used for on-chip clock generation, then some meansof disabling or bypassing he PLL should be provided. This bypass makes chip testing and debugeasier.2.2 Memory and Memory InterfaceMemories present a special challenge when designing for reuse. In FPGA designs, memories aregenerally designed using vendor-supplied modules or module generators, making them verytechnology dependent. Memory compilers developed for ASICs are not currently designed totarget FPGA architectures. However, some synthesis tools can recognize RAM from RTL code,making the design synthesis-tool dependent and FPGA-vendor independent.2.2.1 On-Chip MemoryFPGAs architectures can accommodate small to medium blocks of memory on-chip. Smaller onchipRAM and ROM can be distributed throughout the FPGA by configuring the logic functiongenerators into bit-wide and byte-deep memory (i.e., 16x1, 16x2, 32x1, and 32x2). Distributed